IBM System/370 145 Reference Summary page 91

SYSTEM/370 INSTRUCTION SET
Op
Op
Operation
Mnemonic
Code
Format
Operands Descr1pt1on Interruptions
Cond1t1on Code
Operation Mnemonic Code Format Operands Descnpt1on Interruptions Cond1t1on Code
Branch and BASR 00 RR R1, R2 Store the current Operatmn
Unchanged
Monitor
MC AF SI 01, B1 12 Monitor class spec1- Operation Unchanged
Save v1trual 1nstruct10n Call
tied m bits 12-15 of Spec1f1cat1on Note. New Program
address 1n the GPR
mstrucuon are Interrupt = 40
spec1f1ed by the R1 matched against
field Replace the
Ctrl Reg 8 mask bits.
current PSW address If match occurs, 01,
with data from the
B 1 field 1s stored mto
RZGPR Location '9C'
Branch and BAS
40 Rx A1, 02
Store the current
Operation
Unchanged Move Long MVCL OE RR Fl1,R2 Opr 2 tnto Opr 1 1f Operation
0 = Opr 1, Opr 2 counts
Save
(X2, B21
virtual 1nstruct1on
no overlap. Regs Protection equal
address m the GPR
must be even/odd Addressing 1 = Opr 1 Count Low
spec1f1ed by the R 1 pairs. Even regs
Spec1f1cat1on
2
=
Opr 1 Count High
field Replace the
contain field sources
3
=
Destructive Over-
current
PSW
address
Odd regs contain
lap, No Movement
with the data spec1-
field lengths and
f1ed by the 02 (X2,
padding character
82) storage location
Padding 1s used 1f
Opr 2 shorter than
Compare CLM BO RS R1, M3, QPR 2 compared to Operation 0
=
Bytes Equal or
Opr 1.
Logical 02 (B2) OPR 1 under mask Protection Mask is Zero
Characters
Both operands un· Addressing 1 = First Oper Low
Purge TLB PTLB B2 2-Byte 81 01 The addresses m the Operation Unchanged
Under Mask changed 2 = First Oper High
(Table 00 Op Code
Table Lookas1de Pnv Oper
Lookas1de
Buffers are made
Compare CLCL
OF RR
R1, R2 Oper 1 Compared Operation 0 = Oper are equal or Buffer)
invalid
Logical to QPR 2. Regs Protection field lengths are 0
Long
must be even/odd Addressing 1 = First Oper Low
Reset RRB B2 2-Byte
B1 01
The reference bit
Operation 0 = Ref Bit 0, change Btt 0
pairs Even regs Spec1f1cat1on 2
=
First Oper High
Reference 13 Op Code associated with the Pnv Oper 1
=
Ref Bit 0, Change Btt 1
contain field
Bot 81 01 real address 1s Addressmg 2
=
Ref Bit 1, Change Bit 0
sources.
Odd
regs
set to zero The
3 = Ref Bit 1, Change Bit 1
contain field lengths
cond1t1on code 1s set
and padding charac-
to reflect the previous
ter Operation ter-
status of the reference
minates on mismatch.
and change bits.
Shorter operand ex-
tended with padding Set Clock SCK B204 SI 01 (B11
Eight byte field of Operation 0 = Clock Value Set
character. QPR 1 replaces
Pnv Oper 1
=
Clock Value Secure
value of time of day Protection 2 - - - - - - - - -
1 Insert ICM BF RS R1, M3, QPR 1 selected Operation 0 =All Inserted Bits 0,
Characters 02 (B2) bytes replaced by Protection or Mask o
day dock. Clock Addressmg 3
=
Clock Not Operational
secure switch must Spec1f1cat1on
Under Mask QPR 2 under mask Addressing 1 = First Bit of Inserted be depressed
OPR 2 unchanged. Field One
2 = First Bit of Inserted
Set Clock SCKC B2 2-Byte 81 01
The double word at Operation Unchanged
Field Zero
Comparator 06 Op Code the 81 01 address 1s Priv Oper
stored mto control Addressing
Load LCTL B7 RS R1, R3 OPR 2 loaded m con- Operation Unchanged
Control
02 (B2) trol regs R1 to R3 1n Pnv Oper
ascending order Protection
storage at the current Specif 1cat1on
module location Protection
XXOO, ICKCTDDI
Start1 ng reg spec1- Addressing
f1ed by OPR1, ending
Spec1f1cat1on
reg by QPR 3 Wrap-
around possible
Set CPU SPT B2 2-8yte 81 01 The double word at Operation Unchanged
Timer 08 Op Code the 81 01 address 1s Pnv Oper
SI stored mto control Addressing
storage at the current
Spec1f1cat1on
Load Real LRA B1 Rx R1, 02 Virtual address spec1- Operation
0 = Translation available
Address (X2 B2) tied by X2 02 82 1s
Pnv Oper 1 = Seg Table Entry Invalid
module location
XX/8 (PTI
translated to a rea I Addressing 2 =Page Table Entry Invalid
address and inserted Translation 3 = Seg or Page Table
I mto the GPR spec•- Spec1f1cat1on
Length V1olat1on
f1ed by R1
8.1