IBM System/370 145 Reference Summary page 30

ECCL Board Layout
v
OCPL
'
OCPL
u
T
s
R
a
1862 1862
1862 1862
S0232 S0226 S0244 S0238
SOR SOR SOR SOR
Btts
81t<; Bits Bits
o
B 16
24
Basic 1 9
17 25
System 32
40 48 56
Card 33 41 49
57
1862 1862 1862 1862
S0235
S0229 S0247 S0241
SOR SOR SOR SOR
Bits Bits Bits Bits
2 10 18
26
3 11
19 27
34
42 50 58
35 43 51 59
• Storage stze The mam storage capacity w1thm the CPU frame may
be any of the following
Control
CPU Model Program Storage
Storage
3145FED
114,688 Bytes {112Kl 32K
(See Note)
3145GE 163,840 Bytes (160K)
32K
3145GFD 212,992 Bytes (208K) 32K
3145 H
262, 114 Bytes (256K) 32K
3145HG 393,216 Bytes (384K)*
32K
3145 I 524,288 Bytes (512KJ*
32K
Mam storage capacity above 256K bytes 1s contamed ma
3345 mam storage frame When a main storage frame
JS
attached, 1t contains the low-order storage addresses
NOTE The 3145 has movable control storage boundary that
allows up to 64K (65,536) bytes of control storage, depending
on the feature installed The additmnal control storage capacity
above 32K 1s at the expense of main storage The storage
boundary 1s determined at the time that the microprogram 1s
compiled
Voltage
Locations
On Phase 2 I STG Array Boards
Voltages are apphed to EACH card. Each card occupies two
connector pos1t1ons
+7V
+2V
+1.25V
809
804
003
-3
GND
806
DOB/813
p
6031
S0261
S0262
Read
Check
Bit
Gen
ECCL BOARD LAYOUT
N
M
L K J H G F E D
c
1860
1863 1861
1859 6031 1862 1862 1862
1862 1865 1864
S0301 S0271 S0290 S0280 S0251
S0208 S0202 S0220 S0214 S0312 S0401
S0273 S0273 S0292 S0287 S0257
S0404
SOR SOR SOR SOR
Bits
Bits Bits Bits
Delay
Synd
Line
Gen
#
1
# 1
4 12 20 28
Parity Error
Write
5 13 21 29
Storage
Type
Syndrome
Check
Address
Out
Decoder
36 44 52 60
Gen
Decoder Bit
37 45 53 61
Reg
Gen
1863
1862 1862 1862 1862 1865
S0275
S0211 S0205 S0223 S0217 S0315
S0277
SOR SOR SOR
SOR
Bits Bits Bits Bits
Synd
Delay
Gen
Line
#2
#2
6 14 22 30
7 15 23 31
38
46
54 62
39 47 55
63
DATA BIT LOCATION CHART
v
U T
Q
N M K H G D C B A
34 32 42 40 50 48 58 56 Cl CB 38 36 46 44 54 52 62
eo
Add'
Buffer
Term 35 33 43 41 51 49 59 57 C2
co
39 37 47 45 55 53
63
61 Cacd
Cacd 1341 1321 1421 1401 1501 1481 1581 1561 IC11 ICBI 1381 1361 1461 1441 1541 (521 (621 (601
Wiring Side
v
U T
Q
N M
K
2 0
10J 8
18 16 26 24 C16
=
Term
3 1
11J
g
19 t7 27 25 C4 CT
Ca'd
(2)
(QI (101 (81
(181 1161 (261 1241 (C161 (C32
W1nngS1de
NOTES
t. The 24K BSM has two bits
per card for 18 cards
in lower
rows
2 The 48K BSM has one bit per card for 36 cards
3 24K BSM 1umper P/N 2637601 (red)
4. 48K BSM 1umper P/N 2637602 (yellow)
H G
D A
6 4 14 12 22 20 30 28
Add'
Buffer
7 5 15 13 23 2t 31 29 Ca'd
161 (41 (141 (121 (221 (20
1301 (28)
2.5
B A
1866
S0407
S0410
DCPL
BSM
Clock
OCPL