Analog Devices MAX98380 Manual
Analog Devices MAX98380 Manual

Analog Devices MAX98380 Manual

Small, boosted, digital input class-d amplifier
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MAX98380

General Description

The MAX98380 is a small, mono Class-D audio amplifier
featuring an integrated capacitive boost converter. The
device implements a tripler charge pump-based boost
converter that efficiently delivers up to 4.85W at 1%
THD+N into an 8Ω load. The capacitive boost replaces
the large and expensive inductor required for an inductive
boost with smaller, lower-profile capacitors that reduce the
total PCB solution.
Additionally, as the power-supply voltage varies due to de-
clining battery life, an on-chip limiter (DHT) automatically
optimizes the headroom available to the Class-D amplifier
to maintain consistent distortion and listening levels.
Thermal-foldback protection ensures robust behavior
when the thermal limits of the device are reached. When
enabled, it automatically reduces the output power when
the temperature exceeds a user-specified threshold. This
allows for uninterrupted music playback even at high am-
bient temperatures. Traditional thermal protection is also
available in addition to robust overcurrent protection.
The device provides a PCM interface for audio data and
2
a standard I
C interface for control data communication.
The PCM interface supports audio playback using I
left-justified, and TDM audio data formats. A unique clock-
ing structure eliminates the need for an external master
clock for PCM communication. This reduces EMI and pos-
sible board coupling issues in addition to reducing the size
and pin count.
Active emissions-limiting and edge-rate limiting circuitry
greatly reduce EMI. A filterless spread-spectrum modula-
tion scheme eliminates the need for output filtering found
in traditional Class-D devices and reduces the component
count of the solution.
The IC is available in a 0.35mm pitch 24-bump wafer-level
package (WLP). It is specified over the extended, -40°C to
+85°C temperature range.

Applications

● Smartphones
● Smart Speakers
● IoT Devices
● Tablets
SMBus is a trademark of Intel Corp.
Ordering Information
© 2022 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887 U.S.A. | Tel: 781.329.4700 | © 2022 Analog Devices, Inc. All rights reserved.
Arrow.com.
Downloaded from
Small, Boosted, Digital Input Class-D Amplifier
appears at end of data sheet.
Click
here
to ask an associate for production status of specific part numbers.

Benefits and Features

● Integrated Capacitive Boost Converter—No Bulky
Inductors
● 3.6W Output Power into 6Ω at V
● 10mW Total Quiescent Power
● 3ms Turn-On Time
● 80% Efficiency (1.0W into R
● 19.8μV
Speaker Mode Output Noise
RMS
● 16.5μV
Receiver Mode Output Noise
RMS
● Low 0.005% THD+N at 1kHz
● No MCLK Required
● Sample Rates of 8kHz to 192kHz
● Supports Left, Right, or (Left/2 + Right/2) Output in I
and Left-Justified Modes
● Sophisticated Edge Rate Control Enables Filterless
Class-D Outputs
● Low RF Susceptibility Rejects TDMA Noise from GSM
Radios
● Class-D Switching Frequency Trimmed to 10% for
Better EMI Planning
● Extensive Click-and-Pop Reduction Circuitry
● Dynamic Headroom Tracking (DHT)
● Robust Short-Circuit and Thermal Protection
2
S,
● Available in Space-Saving Package: 1.468mm x
2.138mm, 24-Bump WLP (0.35mm Pitch)
EVALUATION KIT AVAILABLE
= 3.7V
BAT
= 8Ω, V
= 3.7V)
L
BAT
2
S
19-101484; Rev 0; 5/22

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Summary of Contents for Analog Devices MAX98380

  • Page 1: General Description

    19-101484; Rev 0; 5/22 © 2022 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887 U.S.A. | Tel: 781.329.4700 | © 2022 Analog Devices, Inc. All rights reserved.
  • Page 2: Simplified Block Diagram

    Small, Boosted, Digital Input Class-D Amplifier Simplified Block Diagram MAX98380 MAX98380 THERMAL DYNAMIC CHARGE PUMP PROTECTION HEADROOM PVDD BOOST / FOLDBACK TRACKING BCLK OUTP LRCLK AUDIO CLASS-D INTERFACE OUTN AMPLIFIER C CONTROL INTERFACE www.analog.com Analog Devices | 2 Arrow.com. Downloaded from...
  • Page 3: Table Of Contents

    DHT Mode 1—Signal Distortion Limiter (SDL) ........... 39 www.analog.com Analog Devices | 3 Arrow.com.
  • Page 4 Revision History ................81 www.analog.com Analog Devices | 4 Arrow.com.
  • Page 5 C Reading n-Bytes of Data from the Slave ..........54 www.analog.com Analog Devices | 5 Arrow.com.
  • Page 6 Table 7. Component List ............... . . 79 www.analog.com Analog Devices | 6 Arrow.com.
  • Page 7: Absolute Maximum Ratings

    Supply Voltage performance is not guaranteed Supply Voltage Guaranteed by PSRR test 1.71 1.89 Range rising Undervoltage UVLO Lockout falling = +25°C, BST_BYPASS_MODE = 0 Quiescent Power = +25°C, BST_BYPASS_MODE = 1 www.analog.com Analog Devices | 7 Arrow.com. Downloaded from...
  • Page 8 = 1.0W, BST_BYPASS_MO DE = 0 f = 1kHz, Z 8Ω + 33µH = 0.8W, BST_BYPASS_MO DE = 1 CHARGE PUMP BOOST CONVERTER Maximum Soft-Start CP_SOFT_TIMER = 0x3, nominal caps 1.725 Time (2x2.2μF/2x2.2μF) www.analog.com Analog Devices | 8 Arrow.com. Downloaded from...
  • Page 9 Z = 8Ω + 33μH or 6Ω + 33μH = +25°C, digital silence used for input Supply Rejection PSRR signal, Z = ∞, DC, V = 1.71V to 1.89V www.analog.com Analog Devices | 9 Arrow.com. Downloaded from...
  • Page 10 = 1kHz, T THD+N = 8Ω + 33µH Distortion + Noise +25°C = 500mW, = 6Ω + 33µH, BST_BYPASS_MO DE = 1 Intermodulation ITU-R, 19kHz/20kHz, 1:1, V = -3dBFS, Distortion = 8Ω + 33μH www.analog.com Analog Devices | 10 Arrow.com. Downloaded from...
  • Page 11 , referenced to signal level at Passband Ripple δ -0.1 +0.1 1kHz Stopband Cutoff Attenuation > δ 0.49 x f Stopband Attenuation δ f > f Group Delay f = 1kHz samples www.analog.com Analog Devices | 11 Arrow.com. Downloaded from...
  • Page 12 Internal Pulldown BCLK, LRCLK and DIN MΩ Resistance DIGITAL I/O / INPUT—RESET 0.75 x Input Voltage High 0.25 x Input Voltage Low Input Leakage Current µA Input Hysteresis Note 3 Maximum Input Capacitance www.analog.com Analog Devices | 12 Arrow.com. Downloaded from...
  • Page 13 DIN Frame Delay After Measured in number of BCLK cycles, set cycles LRCLK Edge by selected TDM mode C INTERFACE TIMING Serial Clock Frequency 1000 Bus Free Time Between STOP and START µs Conditions www.analog.com Analog Devices | 13 Arrow.com. Downloaded from...
  • Page 14 Valid Clock Frequencies sections for more information. Note 3: Minimum and/or maximum limit is guaranteed by design and by statistical analysis of device characterization data. The specification is not guaranteed by production testing. www.analog.com Analog Devices | 14 Arrow.com. Downloaded from...
  • Page 15: Typical Operating Characteristics

    = 1kHz f = 1kHz f = 100Hz f = 100Hz f = 100Hz -100 -100 -100 0.001 0.01 0.001 0.01 0.001 0.01 OUTPUT POWER (W) OUTPUT POWER (W) OUTPUT POWER (W) www.analog.com Analog Devices | 15 Arrow.com. Downloaded from...
  • Page 16 = 1kHz f = 1kHz f = 100Hz f = 100Hz f = 100Hz -100 -100 -100 0.001 0.01 0.001 0.01 0.001 0.01 OUTPUT POWER (W) OUTPUT POWER (W) OUTPUT POWER (W) www.analog.com Analog Devices | 16 Arrow.com. Downloaded from...
  • Page 17 THERMAL FOLDBACK ENABLED THERMAL FOLDBACK ENABLED THERMAL FOLDBACK ENGAGED THERMAL FOLDBACK ENGAGED 10% THD+N 10% THD+N 10% THD+N 1% THD+N 1% THD+N 1% THD+N LOAD IMPEDANCE (Ω) LOAD IMPEDANCE (Ω) LOAD IMPEDANCE (Ω) www.analog.com Analog Devices | 17 Arrow.com. Downloaded from...
  • Page 18 DEFAULT CAPACITORS CP_CLK_SEL = 0x0 CP_CLK_SEL= 0x0 = 3.7V = 8Ω + 33μH DEFAULT CAPACITORS CP_CLK_SEL= 0x0 0.0001 0.001 0.01 0.0001 0.001 0.01 OUTPUT POWER (W) OUTPUT POWER (W) OUTPUT POWER (W) www.analog.com Analog Devices | 18 Arrow.com. Downloaded from...
  • Page 19 CP_CLK_SEL = 0x0 CP_CLK_SEL = 0 = 3.7V = 6Ω + 33μH DOUBLE FLYING CAPACITORS CP_CLK_SEL = 0x2 0.0001 0.001 0.01 0.0001 0.001 0.01 OUTPUT POWER (W) OUTPUT POWER (W) OUTPUT POWER (W) www.analog.com Analog Devices | 19 Arrow.com. Downloaded from...
  • Page 20 CP_CLK_SEL = 0x2 CP_CLK_SEL = 0x2 = 4.4V = 8Ω + 33μH DOUBLE FLYING CAPACITORS CP_CLK_SEL = 0x2 0.0001 0.001 0.01 0.0001 0.001 0.01 OUTPUT POWER (W) OUTPUT POWER (W) OUTPUT POWER (W) www.analog.com Analog Devices | 20 Arrow.com. Downloaded from...
  • Page 21 CP_CLK_SEL = 0x3 CP_CLK_SEL = 0x3 = 4.4V = 6Ω + 33μH OVERSIZED CAPACITORS CP_CLK_SEL = 0x3 0.0001 0.001 0.01 0.0001 0.001 0.01 OUTPUT POWER (W) OUTPUT POWER (W) OUTPUT POWER (W) www.analog.com Analog Devices | 21 Arrow.com. Downloaded from...
  • Page 22 WITH RAMPING DISABLED WITH RAMPING DISABLED WITH RAMPING ENABLED WITH RAMPING ENABLED toc70 toc71 toc72 1V/div 1V/div 1V/div 5V/div 5V/div 5V/div FOUTP FOUTP FOUTP OUTPUT OUTPUT OUTPUT 2V/div 2V/div 2V/div 2ms/div 2ms/div 2ms/div www.analog.com Analog Devices | 22 Arrow.com. Downloaded from...
  • Page 23 OUTPUT LEVEL NORMALIZED TO 1kHz OUTPUT LEVEL NORMALIZED TO 1kHz = 8Ω + 33μH = 8Ω + 33μH = 8Ω + 33μH = 176.4kHz = 88.2kHz = 8kHz FREQUENCY (kHz) FREQUENCY (kHz) FREQUENCY (kHz) www.analog.com Analog Devices | 23 Arrow.com. Downloaded from...
  • Page 24 SAMPLE RATE = 44.1kHz SAMPLE RATE = 8kHz SAMPLE RATE = 8kHz SMALL SIGNAL LARGE SIGNAL SMALL SIGNAL -100 -100 -100 -120 -120 -120 -140 -140 -140 FREQUENCY (kHz) FREQUENCY (kHz) FREQUENCY (kHz) www.analog.com Analog Devices | 24 Arrow.com. Downloaded from...
  • Page 25 1000 0.01 1000 FREQUENCY (kHz) FREQUENCY (kHz) LOAD CURRENT (mA) PVDD WIDEBAND PVDD WIDEBAND OUTPUT SPECTRUM OUTPUT SPECTRUM toc94 = OPEN CP_CLK_SEL = 0x0 -100 -120 -140 -160 0.01 1000 FREQUENCY (kHz) www.analog.com Analog Devices | 25 Arrow.com. Downloaded from...
  • Page 26: Pin Configuration

    Charge Pump 1st and 2nd Flying Capacitor Negative Terminal — CP2P Charge Pump 2nd Flying Capacitor Positive Terminal — CPBYP Charge Pump Bypass — PVDD Charge Pump Output. Speaker amplifier power supply. — Supply www.analog.com Analog Devices | 26 Arrow.com. Downloaded from...
  • Page 27 PCM Interface Frame Clock Input/Output. LRCLK frequency LRCLK matches the PCM interface sample rate. Internally pulled down to Digital Input GND through R PCM Interface Data Input. Internally pulled down to GND through Digital Input www.analog.com Analog Devices | 27 Arrow.com. Downloaded from...
  • Page 28: Functional Diagrams

    INTERFACE MANAGEMENT UVLO THERMAL PROTECTION MEAS CONTROL REGISTERS / FOLDBACK CLOCK AND DATA DYNAMIC HEADROOM MONITORING TRACKING OUTP DIGITAL FILTERS & CLASS-D BCLK INTERFACE SIGNAL PROCESSING AMPLIFIER OUTN LRCLK MAX98380 MAX98380 PGND www.analog.com Analog Devices | 28 Arrow.com. Downloaded from...
  • Page 29: Detailed Description

    (LRCLK frequency), the configured clock ratio cannot result in a BLCK frequency that exceeds 24.576MHz. PCM Data Format Configuration The device supports the standard I S, left-justified, and TDM data formats, and the operating mode is configured using www.analog.com Analog Devices | 29 Arrow.com. Downloaded from...
  • Page 30: I 2 S/Left-Justified Mode

    14 14 13 13 12 12 11 11 10 10 15 15 14 14 13 13 12 12 11 11 10 10 15 15 14 14 13 13 Figure 2. Left-Justified Mode www.analog.com Analog Devices | 30 Arrow.com. Downloaded from...
  • Page 31: Tdm Modes

    96kHz to avoid violating the BCLK frequency limit of 24.576MHz. Table 2. Supported TDM Mode Configurations INPUT DATA WORD SIZES BCLK TO LRCLK RATIO MAXIMUM SPEAKER PLAYBACK SAMPLE DATA (PCM_DATA_WIDTH) (PCM_BSEL) RATE (FLRCLK) CHANNELS 192kHz 96kHz www.analog.com Analog Devices | 31 Arrow.com. Downloaded from...
  • Page 32 BCLK edge that is used for data capture and data output. The data output is valid on the same active BCLK edge as the data input. The data output also transitions on the same edge as data input. www.analog.com Analog Devices | 32 Arrow.com. Downloaded from...
  • Page 33: Pcm Data Path Configuration

    PCM_DMMIX_CH0_SOURCE and PCM_DMMIX_CH1_SOURCE bits select which of the 16 PCM input channels are used as the input to the mono mixer. In I S and left-justified modes, only 2 input data channels are available www.analog.com Analog Devices | 33 Arrow.com. Downloaded from...
  • Page 34: Pcm Interface Timing

    The IC uses the status register to report the status of various device functions. The status register bits are set when their respective events occur, and are cleared upon reading the register. Device status can be determined by poling the status www.analog.com Analog Devices | 34 Arrow.com. Downloaded from...
  • Page 35: Speaker Path

    The source input data to the speaker amplifier path is routed from the PCM interface. The data is then routed through digital filters, signal processing, and volume/gain control blocks before reaching the Class-D speaker amplifier. www.analog.com Analog Devices | 35 Arrow.com. Downloaded from...
  • Page 36: Speaker Path Dither

    The DAC features a digital lowpass filter that is automatically configured based on the sample rate that is used. This filter eliminates the effect of aliasing and any other high-frequency noise that might otherwise be present. See the DAC Digital Filters section of the Electrical Characteristics table. www.analog.com Analog Devices | 36 Arrow.com. Downloaded from...
  • Page 37: Dynamic Headroom Tracking (Dht)

    DHT thresholds and parameters are calculated relative to the full-scale V The second parameter is the measured speaker amplifier supply voltage level (V ). The measurement ADC provides the DHT block with the PVDD supply voltage level (V PVDD www.analog.com Analog Devices | 37 Arrow.com. Downloaded from...
  • Page 38: Figure 10. Vtpo And Atpo Calculation Example

    = 13.63V ≈ -3dB = 9.65V (SUP = -20%) = 8.04V INPUT SIGNAL LEVEL (dBFS) 0dBFS Figure 10. V TPO and A TPO Calculation Example www.analog.com Analog Devices | 38 Arrow.com. Downloaded from...
  • Page 39: Dht Mode 1-Signal Distortion Limiter (Sdl)

    = +20% DHT SDL ACTIVE: INFINITY:1 COMPRESSOR INPUT SIGNAL LEVEL (dBFS IN LINEAR SCALE) 0dBFS Figure 11. Signal Distortion Limiter with V MPO ≤ V SUP and +20% Headroom (SUP HR ) www.analog.com Analog Devices | 39 Arrow.com. Downloaded from...
  • Page 40: Figure 12. Signal Distortion Limiter With Vmpo ≤ Vsup And 0% Headroom (Sup Hr )

    = 0% DHT SDL INACTIVE: SUFFICIENT HEADROOM INPUT SIGNAL LEVEL (dBFS IN LINEAR SCALE) = 0dBFS Figure 12. Signal Distortion Limiter with V MPO ≤ V SUP and 0% Headroom (SUP HR ) www.analog.com Analog Devices | 40 Arrow.com. Downloaded from...
  • Page 41: Figure 13. Signal Distortion Limiter With Vmpo ≤ Vsup And -20% Headroom (Sup Hr )

    ) proportionally scales down. In cases with zero or positive amplifier supply headroom settings (+20% ≥ ≥ 0%), the input signal level can exceed the SDL rotation point (SDL ) before the peak output exceeds V In this case, amplifier output clipping can be prevented. www.analog.com Analog Devices | 41 Arrow.com. Downloaded from...
  • Page 42: Figure 14. Signal Distortion Limiter With Vmpo > Vsup And +20% Headroom (Sup Hr )

    = 0% DHT SDL ACTIVE: INFINITY:1 COMPRESSOR INPUT SIGNAL LEVEL 0dBFS (dBFS IN LINEAR SCALE) Figure 15. Signal Distortion Limiter with V MPO > V SUP and 0% Headroom (SUP HR ) www.analog.com Analog Devices | 42 Arrow.com. Downloaded from...
  • Page 43: Dht Mode 2-Signal Level Limiter (Sll)

    SLL threshold (SLL ). As a result of the fixed SLL threshold and rotation point, the transfer function is identical for any V level and corresponding V that is greater than V www.analog.com Analog Devices | 43 Arrow.com. Downloaded from...
  • Page 44: Figure 17. Signal Level Limiter With Vtpo > Vsll As Vsup Decreases

    ). For simplicity, V (SUP = 0%), and has decreased further and is now less than V . As a result, the amplifier output clips before the SLL digitally limits the signal level. www.analog.com Analog Devices | 44 Arrow.com. Downloaded from...
  • Page 45: Dht Attenuation

    . As a result, past this point, the audio signal (in the digital domain) begins to increase. This results in the distortion increasing at the amplifier output (which was already clipping at the limited level of distortion). www.analog.com Analog Devices | 45 Arrow.com. Downloaded from...
  • Page 46: Figure 19. Distortion Limiter Case With -20% Headroom And Amax Exceeded

    ) before the input signal reaches full-scale. Past this point, the audio signal (in the digital domain) begins increasing and the signal level (and any distortion) at the amplifier output increases as well. In this case, the amplifier output was not clipping until after A was exceeded. www.analog.com Analog Devices | 46 Arrow.com. Downloaded from...
  • Page 47: Dht Ballistics

    Charge Pump Boost The MAX98380 features a charge pump tripler that boosts the V supply voltage to PVDD to power the Class-D speaker amplifier. The device features a soft-start sequence to minimize inrush current and voltage overshoot on power- up.
  • Page 48: Speaker Amplifier

    When entering shutdown or standby, the differential speaker outputs simultaneously go to Hi-Z. The comprehensive click-and-pop suppression of the MAX98380 is unaffected by power-up or power-down sequencing. Applying or removing the clocks before or after the transition of RESET yields the same click-and-pop performance.
  • Page 49: Measurement Adc

    When the device is active, the measurement ADC thermal channel is automatically enabled and monitors die temperature to ensure that it does not exceed the configured thermal thresholds. Thermal Warning and Thermal Shutdown Configuration The thermal-warning threshold is configured by the THERMWARN_THRESH[5:0] bit field and the thermal-shutdown www.analog.com Analog Devices | 49 Arrow.com. Downloaded from...
  • Page 50: Thermal Shutdown Recovery Configuration

    (Sr) condition and a STOP (P) condition. Each word transmitted to the IC is 8 bits long and is followed by an acknowledge clock pulse. A master reading data from the IC transmits the proper slave address followed by a series of nine SCL www.analog.com Analog Devices | 50 Arrow.com. Downloaded from...
  • Page 51: Bit Transfer

    STOP condition. SU,STA SU,DAT HD,STA SU,STO HD,DAT HIGH HD,STA START START STOP REPEATED START CONDITION CONDITION CONDITION CONDITION Figure 22. I 2 C START, STOP, and REPEATED START Conditions www.analog.com Analog Devices | 51 Arrow.com. Downloaded from...
  • Page 52: Early Stop Conditions

    The address pointer auto increments to the next register address after each received data byte. This auto-increment feature allows a master to write to sequential registers within one continuous frame. The master signals the end of transmission by issuing a STOP condition. www.analog.com Analog Devices | 52 Arrow.com. Downloaded from...
  • Page 53: Read Data Format

    The master acknowledges receipt of each read byte during the acknowledge clock pulse. The master must acknowledge all correctly received bytes except the last byte. The final byte must be followed by a not acknowledge from the master and then a STOP condition. www.analog.com Analog Devices | 53 Arrow.com. Downloaded from...
  • Page 54: I 2 C Register Map

    WRITE ACCESS RESTRICTIONS BIT FIELD WRITE “RES” TYPE ACCESS SYMBOL DESCRIPTION CONDITION Read Read — — — Only Write Dynamic — — — or Read/ Restricted Device in Software Shutdown EN = 0 Write www.analog.com Analog Devices | 54 Arrow.com. Downloaded from...
  • Page 55 EN = 0 Shutdown Speaker Amplifier Output and Feedback Disabled SPK_EN = 0 THERMFB_EN Thermal Foldback Disabled Dynamic-Headroom Tracking Disabled DHT_EN = 0 PCM_RX_EN = PCM Interface Data Input and Output Disabled www.analog.com Analog Devices | 55 Arrow.com. Downloaded from...
  • Page 56: Register Map

    – – – – – ChargePump Control 0x2082 SS TIMER ADJUST[7:0] CP_CLK_SEL[1:0] CP_SOFT_TIMER[5:0] Speaker Path Control AMP volume 0x2090 – SPK_VOL[6:0] control[7:0] 0x2091 AMP Path Gain[7:0] – – – – – SPK_GAIN_MAX[2:0] www.analog.com Analog Devices | 56 Arrow.com. Downloaded from...
  • Page 57 Meas ADC Lowest 0x20BA PVDD Readback LOWEST_PVDD_DATA[7:0] MSB[7:0] Meas ADC Lowest LOWES 0x20BB PVDD Readback – – – – – – – T_PVDD LSB[7:0] _DATA Meas ADC Highest 0x20BC Temp Readback HIGHEST_TEMP_DATA[7:0] MSB[7:0] www.analog.com Analog Devices | 57 Arrow.com. Downloaded from...
  • Page 58: Register Details

    Writing a 1 resets the device and 0: No action. returns the control registers to their power-on 1: Triggers a software reset event. reset states. Writing a 0 has no effect, and readback always returns 0. www.analog.com Analog Devices | 58 Arrow.com. Downloaded from...
  • Page 59 1 (SPK_EN = 1). The bit is also set when the device enters active state when recovering from a UVLO event when auto-restart bit is set to 1 (VBAT_UVLO_AUTORESTART = 1 or PVDD_UVLO_AUTORESTART = 1). www.analog.com Analog Devices | 59 Arrow.com. Downloaded from...
  • Page 60 0x02: 52°C THERMWAR Sets the thermal warning threshold ...: ... N_THRESH temperature. 0x62: 148°C 0x63: 149°C 0x64-0x7F: 150°C Thermal Shutdown Threshold (0x2021) Field – THERMSHDN_THRESH[6:0] Reset – 0x64 Access – Write, Read Type www.analog.com Analog Devices | 60 Arrow.com. Downloaded from...
  • Page 61 0x1: 10ms/dB foldback attenuation. 0x2: 100ms/dB 0x3: 300ms/dB 0x0: 0.25dB/°C This sets the slope of the thermal foldback THERMFB_S 0x1: 0.5dB/°C attenuation when die temperature exceeds LOPE 0x2: 1.0dB/°C thermal-warning threshold. 0x3: 2.0dB/°C www.analog.com Analog Devices | 61 Arrow.com. Downloaded from...
  • Page 62 Enables the internal speaker protection 0x0: Disables internal speaker data monitor. monitor. 0x1: Enables internal speaker data monitor. Enables the clock monitor to monitor PCM 0x0: Disable CMON_EN input clocks for clock errors. 0x1: Enable www.analog.com Analog Devices | 62 Arrow.com. Downloaded from...
  • Page 63 0: Input data captured and output data valid on PCM_BCLKE rising edge of BCLK. Selects the active BCLK edge. 1: Input data captured and output data valid on falling edge of BCLK. www.analog.com Analog Devices | 63 Arrow.com. Downloaded from...
  • Page 64 0x0: Output of mono mixer is Channel 0. 0x1: Output of mono mixer is Channel 1. PCM_DMMI Determines the behavior of the mono mixer 0x2: Output of mono mixer is (Channel 0 + X_CFG circuit. Channel 1)/2. 0x3: Reserved. www.analog.com Analog Devices | 64 Arrow.com. Downloaded from...
  • Page 65 0x0: 1.024Mhz (normal mode) and 64kHz (low- power mode) CP_CLK_SE Configures the frequency of the charge pump 0x1: 2/3 x Default frequency clock. 0x2: 1/2 x Default frequency 0x3: 1/3 x Default frequency www.analog.com Analog Devices | 65 Arrow.com. Downloaded from...
  • Page 66 BITFIELD BITS DESCRIPTION DECODE 0x00: 0dB 0x01: -0.5dB 0x02: -1.0dB Sets the digital volume level of the speaker ...: (-0.5dB steps) SPK_VOL amplifier path. 0x7C: -62.0dB 0x7D: -62.5dB 0x7E: -63dB 0x7F: Mute www.analog.com Analog Devices | 66 Arrow.com. Downloaded from...
  • Page 67 1: DC blocking filter enabled. AMP SSM Configuration (0x2094) BST_BYP_ AMP_SSM_ Field – – – – SPK_SSM_MOD[1:0] MODE Reset – – – – Access – – – – Write, Read Write, Read Write, Read Type www.analog.com Analog Devices | 67 Arrow.com. Downloaded from...
  • Page 68 0x1: Speaker amplifier is enabled. Meas ADC Sample Rate (0x20B0) Field – – – – – – MEAS_ADC_SR[1:0] Reset – – – – – – Access – – – – – – Write, Read Type www.analog.com Analog Devices | 68 Arrow.com. Downloaded from...
  • Page 69 1: Filter is applied. Value: Measurement ADC channel cutoff frequencies 0x0: 7.5kHz MEAS_ADC_ Sets the PVDD channel lowpass filter 0x1: 20kHz PVDD_FILT_ bandwidth. 0x2: 75kHz (default) COEFF 0x3: 150kHz 0x4: 300kHz 0x5 to 0xF: Reserved www.analog.com Analog Devices | 69 Arrow.com. Downloaded from...
  • Page 70 MEAS_ADC MEAS_ADC Field – – – – – _THERM_R – _PVDD_RD D_UPD _UPD Reset – – – – – – Access – – – – – Write Only – Write Only Type www.analog.com Analog Devices | 70 Arrow.com. Downloaded from...
  • Page 71 MEAS_ADC_ Provides the measured PVDD value. PVDD_DATA 9-Bit mode: Measured V (V) = PVDD MEAS_ADC_PVDD_DATA[8:0] x 29.3mV Meas ADC Temp Readback MSB (0x20B8) Field MEAS_ADC_THERM_DATA[8:1] Reset 0x00 Access Read Only Type www.analog.com Analog Devices | 71 Arrow.com. Downloaded from...
  • Page 72 Meas ADC Lowest PVDD Readback LSB (0x20BB) LOWEST_P Field – – – – – – – VDD_DATA Reset – – – – – – – Access – – – – – – – Read, Ext Type www.analog.com Analog Devices | 72 Arrow.com. Downloaded from...
  • Page 73 Meas ADC Config (0x20CF) MEAS_ADC Field – – – – – – – _PVDD_EN Reset – – – – – – – Access – – – – – – – Write, Read Type www.analog.com Analog Devices | 73 Arrow.com. Downloaded from...
  • Page 74 0: Signal distortion limiter mode where limiter DHT_LIM_M Selects whether the DHT limiter is in signal threshold tracks supply. distortion or signal level limiter mode. 1: Signal level limiter mode where limiter uses fixed thresholds. www.analog.com Analog Devices | 74 Arrow.com. Downloaded from...
  • Page 75 0x3: 160μs/dB 0x4: 320μs/dB 0x5: 640μs/dB 0x6: 1.28ms/dB DHT_ATK_R 0x7: 2.56ms/dB Selects the DHT attack rate. 0x8: 5.12ms/dB 0x9: 10.24ms/dB 0xA: 20.48ms/dB 0xB: 40.96ms/dB 0xC: 81.92ms/dB 0xD: 163.84ms/dB 0xE: Reserved 0xF: Reserved www.analog.com Analog Devices | 75 Arrow.com. Downloaded from...
  • Page 76 0x5: 8 LSB 0x6: 10 LSB 0x7: 12 LSB 0x8: Reserved DHT_SUPPL Select whether PVDD DHT hysteresis is 0: DHT is disabled. Y_HYST_EN enabled or disabled. 1: DHT is enabled. www.analog.com Analog Devices | 76 Arrow.com. Downloaded from...
  • Page 77 – Type Read, Ext BITFIELD BITS DESCRIPTION DECODE Disable or enable all blocks and reset all logic 0: Device powered down. except the I C interface and control registers. 1: Device enabled. www.analog.com Analog Devices | 77 Arrow.com. Downloaded from...
  • Page 78 Small, Boosted, Digital Input Class-D Amplifier Revision ID (0x21FF) Field REV_ID[7:0] Reset 0x40 Access Read Only Type BITFIELD BITS DESCRIPTION DECODE Revision of the device. Updated at every REV_ID 0x41: Device revision — RevA0 silicon device revision. www.analog.com Analog Devices | 78 Arrow.com. Downloaded from...
  • Page 79: Applications Information

    2.2μF ± 10% 0402 CP2P 2.2μF ± 10% 0402 CP2P 2.2μF ± 10% 0402 CPBYP 0.1μF ± 10% 0201 CPBYP 2.2μF ± 10% 0402 CPBYP 2.2μF ± 10% 0402 1μF ± 20% 0201 www.analog.com Analog Devices | 79 Arrow.com. Downloaded from...
  • Page 80: Typical Application Circuits

    LRCLK PGND Ordering Information PART NUMBER TEMP RANGE PIN-PACKAGE TOP MARKING MAX98380EWG+ -40°C to +85°C 24 WLP MAX98380EWG+T -40°C to +85°C 24 WLP +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. www.analog.com Analog Devices | 80 Arrow.com. Downloaded from...
  • Page 81: Revision History

    Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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