Analog Devices MAX98388 Manual
Analog Devices MAX98388 Manual

Analog Devices MAX98388 Manual

Digital input class-d amplifier with iv feedback and brownout protection

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Digital Input Class-D Amplifier with
IV Feedback and Brownout Protection
General Description
The MAX98388/MAX98389 is a small, cost-effective
mono digital input amplifier with integrated IV feedback.
The device operates over a wide supply voltage range
from 2.3V to 10V. With this supply range, both versions
support
single-cell,
two-cell,
regulated/boosted portable applications. MAX98388 is
optimized for up to 5.5V applications (single-cell), while
MAX98389 is optimized for 5V to 10V cases (two-cell).
The Class-D playback amplifier pairs Class-AB level
audio performance with the efficiency needed to extend
battery life in portable applications. Active emissions-
limiting (AEL) and edge-rate limiting circuitry combined
with a spread-spectrum modulation (SSM) scheme
reduces EMI and eliminates the need for the output
filtering required for traditional Class-D amplifiers.
The device provides a precision output current sense
channel and an output voltage feedback channel. The
data collected by these channels can be transmitted on
the audio data output and enables algorithms such as
audio enhancement, bass boosting, speaker protection,
and haptic functions to be run on the host audio DSP.
The device includes a programmable threshold playback
channel ALC that provides brownout protection for
batteries in portable systems, and robust thermal and
overcurrent protection to prevent device damage.
The device provides a PCM interface for audio playback
and IV feedback data and pairs this with a standard I
interface for device control and status readback. The
PCM interface supports common audio data formats
2
such as I
S, left justified, and TDM timing. A unique
clocking structure eliminates the need for an external
high-frequency reference clock. In addition to reducing
device size and pin count, eliminating this clock saves
interface power while reducing the risk of EMI from high-
speed switching and potential board coupling issues.
The package connections are designed to only require
edge routing, allowing the use of the cost-effective
wafer-level package (WLP) with no requirement for
expensive bump vias. The device is available in a 0.4mm
pitch 16-bump WLP package and is specified over the
extended -40°C to +85°C temperature range.
SMBus is a trademark of Intel Corp.
© 2023 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
Click
here
to ask an associate for production status of specific part numbers.
Benefits and Features
and
externally
2
C
Applications
Ordering Information
MAX98388/MAX98389
Wide Amplifier Supply Range (2.3V to 10V)
• Supports Both Single-Cell and Two-Cell Cases
High-Performance Class-D Amplifier
• Up to 111dB Dynamic Range (A-Weighted)
• 10μV
Output Noise (Single-Cell Mode)
RMS
• 14.5μV
Output Noise (Two-Cell Mode)
RMS
High Output Power (THD+N ≤ 1%)
• 1.32W Output Power into 4Ω (V
• 2.4W Output Power into 4Ω (V
• 5.15W Output Power into 4Ω (V
• 9.1W Output Power into 4Ω (V
High Amplifier Efficiency (Playback Only Power)
• 76% Efficiency at 0.1W into 4Ω (V
• 85.5% Efficiency at 1W into 4Ω (V
• 90% Efficiency at 1W into 8Ω (V
Peak THD+N Better than -83dB at 1kHz
Low Total Quiescent Power
• 9.3mW (V
= 3.7V, IV Feedback Disabled)
PVDD
• 13.9mW (V
= 3.7V, IV Feedback Enabled)
PVDD
• 16.1mW (V
= 5V, IV Feedback Enabled)
PVDD
• 22.5mW (V
= 7.4V, IV Feedback Enabled)
PVDD
Low < 5µW Software Shutdown Power
1ms Turn-On Time (f
= 48kHz, Ramp Disabled)
S
Five Sample Playback Delay (f
No External Reference Clock Required
Playback Sample Rates from 8kHz to 96kHz
Trimmed Class-D Switching Frequency for EMI Planning
Extensive Click-and-Pop Reduction Circuitry
Programmable ALC for Brownout Protection
Robust Short-Circuit and Thermal Protection
Available in Space-Saving Package:
2
• 2.93mm
, 16-pin WLP (0.4mm Pitch)
AR/VR Wearables
LRA Haptic Drive
Smart Watches and IoT Devices
Gaming Devices
Notebooks and Tablets
appears at end of data sheet.
= 3.7V)
PVDD
= 5V)
PVDD
= 7.4V)
PVDD
= 10V)
PVDD
= 5V)
PVDD
= 5V)
PVDD
= 5V)
PVDD
< 50kHz, f
= 1kHz)
S
IN
19-101683; Rev 0; 3/23

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Summary of Contents for Analog Devices MAX98388

  • Page 1 Notebooks and Tablets Ordering Information appears at end of data sheet. SMBus is a trademark of Intel Corp. 19-101683; Rev 0; 3/23 © 2023 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
  • Page 2 (2.3V TO 10V) RESET BROWNOUT POWER/STATE THERMAL C CONTROL C SLAVE PROTECTION MANAGEMENT PROTECTION INTERFACE PLAY BACK CLASS-D CHANNEL VOLTAGE MAX98388 PCM AUDIO FEEDB ACK S/TDM) SPEAK ER INTERFACE MAX98389 CHANNEL OUTPUT SENSE SENSE FEEDB ACK CHANNEL www.analog.com Analog Devices | 2...
  • Page 3 RoHS status. Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. www.analog.com Analog Devices | 3...
  • Page 4 IV feedback enabled 4.83 POWER CONSUMPTION / SOFTWARE SHUTDOWN POWER CONSUMPTION = 3.7V, PVDD No toggling on single-cell mode PVDD Software PCM interface pins, µA PVDD_SWSD = 7.4V, Shutdown Current PVDD = +25°C two-cell mode www.analog.com Analog Devices | 4...
  • Page 5 Ripple < δ Passband Cutoff Frequency 0.457 x Droop < -3dB < f , referenced to signal level at δ Passband Ripple -0.1 +0.1 1kHz, digital filter response only Stopband Cutoff 0.49 x Attenuation > δ Frequency www.analog.com Analog Devices | 5...
  • Page 6 = 8Ω + 33µH 110.5 DAC low power mode (Note 3) Dynamic Range A-weighted, 24-bit or 32-bit data, two- cell mode, V PVDD = 8Ω + 33µH = 7.4V, DAC high- performance mode (Note 3) www.analog.com Analog Devices | 6...
  • Page 7 = 8.4V, PVDD 3.87 two-cell mode = 3.7V, PVDD 0.95 single-cell mode = 1kHz, THD+N = 5V, PVDD ≤ 10%, Z = 8Ω 1.72 single-cell mode + 33µH = 7.4V, PVDD 3.75 two-cell mode www.analog.com Analog Devices | 7...
  • Page 8 AC Power Supply PSRR silence used for Rejection Ratio input signal, Z = 10kHz RIPPLE = 8Ω + 33μH or 4Ω + 33μH SPEAKER CLASS-D AMPLIFIER / POWER-SUPPLY INTERMODULATION Power-Supply PVDD supply, = 217Hz, Intermodulation RIPPLE www.analog.com Analog Devices | 8...
  • Page 9 Droop < -3dB, 88.2kHz ≤ f ≤ 96kHz 0.58 Lowpass Filter -40dB limit Stopband Frequency Lowpass Filter Stopband Attenuation = 1kHz Samples Group Delay SPEAKER OUTPUT CURRENT SENSE ADC (Note 2) Resolution Bits Sample Rate S_ISNS Current Range ±3 www.analog.com Analog Devices | 9...
  • Page 10 = 1kHz Current Sense Channel 0.05 Samples Phase Mismatch SPEAKER OUTPUT CURRENT ADC / DIGITAL FILTER CHARACTERISTICS (f < 50 kHz) (Note 2) ≤ f Passband Ripple -0.225 +0.225 Lowpass Filter Cutoff 0.44 -3dB limit Frequency www.analog.com Analog Devices | 10...
  • Page 11 Brownout Voltage Threshold Range Minimum threshold PVDD falling, two- setting cell mode Maximum threshold 7.25 setting Single-cell mode, MAX98388 (Note 4) Brownout Voltage Threshold Hysteresis Two-cell mode, MAX98389 (Note 4) Single-cell mode, All brownout Brownout Voltage MAX98388 voltage threshold Threshold Accuracy...
  • Page 12 High-Frequency Jitter reduction in THD+N, RMS jitter > 40kHz PCM DIGITAL AUDIO INTERFACE / CLOCK AND DATA INPUT TIMING LRCLK to BCLK Active SYNCSET Edge Setup Time LRCLK to BCLK Active SYNCHOLD Edge Hold Time www.analog.com Analog Devices | 12...
  • Page 13 Measured using the EIAJ method with a -60dBFS output signal at 1kHz referenced to output power at 1% THD+N. Note 4: Minimum and/or maximum limit is guaranteed by design and by statistical analysis of device characterization data. The specification is not guaranteed by production testing. www.analog.com Analog Devices | 13...
  • Page 14 TDM 1 MODE WI TH RI SING EDGE SYNC PULSE (LRCLK) AND FALLING ACTIVE EDGE BIT CLOCK (BCLK) DC x t (1-DC) x t BCLK BCLK BCLK BCLK SYNCSET SYNCHOLD LRCLK SETUP HOLD MSB CHANNEL 0 Figure 3. PCM Interface Timing Diagram for TDM 1 Mode www.analog.com Analog Devices | 14...
  • Page 15 Figure 4. PCM Interface Data Output Timing Diagram SU,DAT HD,DAT SU,STA HD,STA SU,STO HIGH START HD,STA CONDITION (S) START REPEATED START STOP CONDITION (S) CONDITION (SR) CONDITION (P) Figure 5. I C Peripheral Device Control Interface Timing Diagram www.analog.com Analog Devices | 15...
  • Page 16 PVDD = 3.072MHz, f = 48kHz, Playback Data Word Size ≥ 24-Bit, Z = Open between OUTP and OUTN, T = +25°C) BCLK LRCLK toc01 toc02 toc03 toc04 toc05 toc06 RESET toc07 toc08 toc09 RESET www.analog.com Analog Devices | 16...
  • Page 17 PVDD PGND PVDD = 3.072MHz, f = 48kHz, Playback Data Word Size ≥ 24-Bit, Z = Open between OUTP and OUTN, T = +25°C) BCLK LRCLK toc10 toc11 toc12 toc13 toc14 toc15 toc16 toc17 toc18 www.analog.com Analog Devices | 17...
  • Page 18 PVDD PGND PVDD = 3.072MHz, f = 48kHz, Playback Data Word Size ≥ 24-Bit, Z = Open between OUTP and OUTN, T = +25°C) BCLK LRCLK toc19 toc20 toc21 toc22 toc23 toc24 toc25 toc26 toc27 www.analog.com Analog Devices | 18...
  • Page 19 PVDD PGND PVDD = 3.072MHz, f = 48kHz, Playback Data Word Size ≥ 24-Bit, Z = Open between OUTP and OUTN, T = +25°C) BCLK LRCLK toc28 toc29 toc30 toc31 toc32 toc33 toc34 toc35 toc36 www.analog.com Analog Devices | 19...
  • Page 20 PVDD PGND PVDD = 3.072MHz, f = 48kHz, Playback Data Word Size ≥ 24-Bit, Z = Open between OUTP and OUTN, T = +25°C) BCLK LRCLK toc38 toc39 toc37 toc40 toc41 toc42 toc43 toc44 toc45 www.analog.com Analog Devices | 20...
  • Page 21 PVDD PGND PVDD = 3.072MHz, f = 48kHz, Playback Data Word Size ≥ 24-Bit, Z = Open between OUTP and OUTN, T = +25°C) BCLK LRCLK toc48 toc46 toc47 toc49 toc50 toc51 toc52 toc53 toc54 www.analog.com Analog Devices | 21...
  • Page 22 PVDD PGND PVDD = 3.072MHz, f = 48kHz, Playback Data Word Size ≥ 24-Bit, Z = Open between OUTP and OUTN, T = +25°C) BCLK LRCLK toc55 toc56 toc57 toc58 toc59 toc60 toc61 toc62 toc63 www.analog.com Analog Devices | 22...
  • Page 23 PVDD PGND PVDD = 3.072MHz, f = 48kHz, Playback Data Word Size ≥ 24-Bit, Z = Open between OUTP and OUTN, T = +25°C) BCLK LRCLK toc64 toc65 toc66 toc67 toc68 toc69 toc70 toc71 toc72 www.analog.com Analog Devices | 23...
  • Page 24 = 10µF + 0.1µF, C = 1µF, PVDD PGND PVDD = 3.072MHz, f = 48kHz, Playback Data Word Size ≥ 24-Bit, Z = Open between OUTP and OUTN, T = +25°C) BCLK LRCLK toc73 toc74 toc75 toc76 toc77 www.analog.com Analog Devices | 24...
  • Page 25 PCB layout. Ground. Ground connection for the internal low voltage analog and digital. — Supply Connect directly to the same ground plane as PGND. Analog OUTP Positive Class-D Amplifier Output PVDD Output www.analog.com Analog Devices | 25...
  • Page 26 PCM Interface Data Output (DOUT). Output Internally Connected. Not used for normal device operation. Leave open or connect to V or GND externally. ADDR can be routed through this bump to I.C. — connect to RESET and V www.analog.com Analog Devices | 26...
  • Page 27 DIGITA L CLASS-D ALC/MUTE CONTROL FILTERS OUTN V FEEDBACK V FEEDBACK MAX98388 DIGITA L COMPENSATI ON FILTERS LRCLK S/TDM) DIGITA L BCLK AUDIO SENSE INTERFACE SENSE SENSE I.C. DIGITA L DOUT COMPENSATI ON FILTERS PGND www.analog.com Analog Devices | 27...
  • Page 28 UVLO threshold to transition from the hardware-shutdown state to the software-shutdown state. The PVDD supply must be above its UVLO threshold to transition from the software-shutdown state to the active state. www.analog.com Analog Devices | 28...
  • Page 29 The device is in the active state with playback active or ready. To avoid errors and Audio Playback audible glitches during any device programming in the active state, all register bit (Active State) field restrictions must be observed. www.analog.com Analog Devices | 29...
  • Page 30 UVLO threshold. None This is the lowest power state. All supplies can be disabled as desired. The device, (Hardware-Shutdown State) all interfaces, and all registers are fully reset in this state. www.analog.com Analog Devices | 30...
  • Page 31 Event that the playback channel is enabled and ready to receive audio data. Indicates that the OTP load routine that OTP Fail OTP_FAIL_* Asserted Level runs when initializing the device has failed to complete successfully. www.analog.com Analog Devices | 31...
  • Page 32 Manual Mode Speaker Indicates that the amplifier output current Amplifier SPK_OVC_* Asserted Level exceeded the overcurrent threshold. Overcurrent Speaker Indicates that an amplifier output clipping Amplifier SPK_CLIP_* Asserted Level event was detected. Clipping www.analog.com Analog Devices | 32...
  • Page 33 The device supports a range of bit-clock-to-frame clock ratios (PCM_BSEL) ranging from 32 to 512. However, based on the selected PCM interface sample rate (LRCLK frequency), the configured clock ratio cannot result in a BLCK frequency that exceeds 24.576MHz. www.analog.com Analog Devices | 33...
  • Page 34 CHANNEL 1 (RIGHT) DOUT PAD BITS PAD BITS BCLK Figure 6. Standard I S Mode Example LRCLK CHANNEL 0 (LEFT) CHANNEL 1 (RIGHT) DOUT PAD BITS PAD BITS BCLK Figure 7. Baseline Left-Justified Mode Example www.analog.com Analog Devices | 34...
  • Page 35 TDM mode configurations for each combination of input data channels and output data slots. In some configurations, the maximum PCM interface and speaker amplifier playback sample rate is limited to less than 96kHz to avoid violating the nominal bit clock (BCLK) frequency limit of 24.576MHz. www.analog.com Analog Devices | 35...
  • Page 36 PCM_BCLKEDGE register bit allows the active bit clock edge (for data capture and data output) to be programmed. The data output is valid on and transitions on the same active bit clock (BCLK) edge as the data input. www.analog.com Analog Devices | 36...
  • Page 37 SLOTS 4 TO 7 SLOTS 8 TO 1 1 SLOTS 12 TO 15 (8 BITS) (8 BITS) (8 BITS) (8 BITS) (8 BITS EACH) (8 BITS EACH) (8 BITS EACH) DOUT BCLK Figure 10. TDM Mode Examples www.analog.com Analog Devices | 37...
  • Page 38 Hi-Z or driven with a 0 code (as set by the PCM_TX_SLOT_HIZ bit field). If a data output is disabled, then the assigned data output slots are either Hi-Z or driven with 0 code (set by the PCM_TX_SLOT_HIZ bit field). www.analog.com Analog Devices | 38...
  • Page 39 DATA 1 (16 BITS) DATA 1 (16 BITS) DATA 1 (16 BITS) DATA 2 (16 BITS) DATA 2 (16 BITS) DATA 2 (16 BITS) DATA 2 (16 BITS) Figure 12. I/V Feedback Shared Channel Data Example www.analog.com Analog Devices | 39...
  • Page 40 The manager terminates transmission, and frees the bus, by issuing a STOP condition. The bus remains active if a REPEATED START condition is generated instead of a STOP condition. START REPEATED START STOP CONDITION (S) CONDITION (Sr) CONDITION (P) Figure 13. I C Peripheral Device Interface START and STOP Condition Example www.analog.com Analog Devices | 40...
  • Page 41 (NACK) is sent when the manager reads the final byte of data and is followed by a STOP condition. START CONDITION (S) CLOCK P ULSE FOR ACKNOWLEDGE NACK (HI GH) ACK (LOW) Figure 14. I C Peripheral Device Interface Acknowledge Bit Example www.analog.com Analog Devices | 41...
  • Page 42 1 BY TE 1 BY TE ADDRESS POINTER AUTO-INCREMENT INTERNAL AUTO-INCREMENT INTERNAL REGISTE R ADDRESS POI NTER REGISTE R ADDRESS POI NTER Figure 16. I C Manager Writing n-Bytes of Data to the Peripheral Device www.analog.com Analog Devices | 42...
  • Page 43 1 BY TE 1 BY TE ADDRESS POINTER AUTO-INCREMENT INTERNAL AUTO-INCREMENT INTERNAL REGISTE R ADDRESS POI NTER REGISTE R ADDRESS POI NTER Figure 18. I C Manager Reading n-Bytes of Data from the Peripheral Device www.analog.com Analog Devices | 43...
  • Page 44 The speaker output signal level for a given digital input signal level is calculated as follows: Output Signal Level (dBV) = Input Signal Level (dBFS) + Digital Volume (dBFS) + 0.5 (dBV) + SPK_GAIN (dB) (0dBFS is referenced to 0dBV or 1V www.analog.com Analog Devices | 44...
  • Page 45 Speaker Amplifier Ultra-Low EMI Filterless Output Traditional Class-D amplifiers require the use of external LC filters or shielding to meet the EN55022B electromagnetic interference (EMI) regulation standards. Analog Devices' active emissions-limiting, edge-rate control circuitry, and spread- spectrum modulation reduce EMI emissions while maintaining high efficiency.
  • Page 46 The clock monitor can be programmed to respond to clock errors in two ways. When the CLOCK_AUTORESTART_EN bit is set to 0, the clock monitor is in manual mode. In manual mode, when a clock error is detected, the clock monitor www.analog.com Analog Devices | 46...
  • Page 47 When a speaker output error is detected, the monitor reports the error status (SPKMON_ERR) and places the device into software shutdown by setting EN to 0. The device remains in software shutdown until the host software sets EN to 1. www.analog.com Analog Devices | 47...
  • Page 48 ALC THRESHOL D TIME AMP LITUDE ATTA CK RELEASE SIGNAL LE VEL SIGNAL LE VEL – ALC_MAX_ATTE N MAX ATTENUATION RELEASE (0dB to -15 dB) DEBOUNCE TIME MUTE TIME Figure 20. Brownout Protection ALC Volume Attenuation Behavior www.analog.com Analog Devices | 48...
  • Page 49 RELEASE DELAY SIGNAL LE VEL SIGNAL LE VEL – ALC_MAX_ATTE N RELEASE DEBOUNCE TIME MUTE UNMUTE (RAMP DIS ABLED) (RAMP DIS ABLED) MUTE TIME Figure 21. Brownout Protection ALC with Mute Enabled with No Ramp www.analog.com Analog Devices | 49...
  • Page 50 MUTE RELEASE DELAY SIGNAL LE VEL SIGNAL LE VEL – ALC_MAX_ATTE N RELEASE DEBOUNCE TIME MUTE UNMUTE (RAMP ENA BLED) (RAMP ENA BLED) MUTE TIME Figure 22. Brownout Protection ALC with Mute Enabled with Ramp www.analog.com Analog Devices | 50...
  • Page 51 SIGNAL LE VEL MUTE UNMUTE (RAMP ENA BLED) (RAMP ENA BLED) RELEASE DEBOUNCE TIME MAX ATTENUATION SET TO 0dB MUTE TIME Figure 23. Brownout Protection ALC with Maximum Attenuation set to 0dB and Mute Enabled with Ramp www.analog.com Analog Devices | 51...
  • Page 52 HOS T REQUE STS ALC RELEASE – HOS T TRIGGERS HAS NO E FFECT ALC MUTE ALC RELEASE (ALC_RLS _TGR) (ALC_RLS _TGR) DISABLED MUTE TIME Figure 24. Brownout Protection ALC with Infinite Hold Enabled and Mute Disabled www.analog.com Analog Devices | 52...
  • Page 53 The behavior of the brownout protection ALC raw status bits relative to the ALC operation state is shown in Figure for a normal case and in Figure 27 for a case with infinite hold enabled. www.analog.com Analog Devices | 53...
  • Page 54 SIGNAL LE VEL – ALC_MAX_ATTE N RELEASE DEBOUNCE TIME MUTE UNMUTE (RAMP ENA BLED) (RAMP ENA BLED) MUTE TIME BR_ALC_ MUTE_RA W Figure 26. Brownout Protection ALC Status Signals for a Case with Mute Enabled with Ramp www.analog.com Analog Devices | 54...
  • Page 55 Once the die temperature drops below the thermal-warning threshold (minus hysteresis), a status indicator is set (thermal warning end), and the amplifier is automatically re-enabled. The global enable (EN = 1) is never changed during thermal shutdown and recovery in automatic mode. www.analog.com Analog Devices | 55...
  • Page 56 Register Default Setting Differences Between MAX98388 and MAX98389 The register map shows the default power-on reset (PoR) settings for the MAX98388. Only one register default setting is different for MAX98389. In register 0x2092, the SPK_AMP_MODE bit defaults to single-cell mode (low) for MAX98388 and to two-cell mode (high) for MAX98389.
  • Page 57: Table Of Contents

    SPK_CLIP_STA – – RESH_STAT _SHDN_STA State TE_STATE TIVE_STATE TATE 2[7:0] Thermal Protection Thermal 0x20 Warning – – – – THERMWARN_THRESH[1:0] THERMSHDN_THRESH[1:0] Threshh old[7:0] Error Monitor Speaker 0x20 SPKMON_THRESH[7:0] Thresho ld[7:0] Speaker 0x20 – SPKMON_LOAD[6:0] Load www.analog.com Analog Devices | 57...
  • Page 58 Setup[7: Sample 0x20 Rate IV_SR[3:0] PCM_SR[3:0] Setup[7: PCM Tx 0x20 Control – – PCM_VMON_SLOT[5:0] 1[7:0] PCM Tx 0x20 Control – – PCM_IMON_SLOT[5:0] 2[7:0] PCM Tx 0x20 PCM_TX_SLOT_HIZ[63:56] Control 1[7:0] PCM Tx 0x20 PCM_TX_SLOT_HIZ[55:48] Control 2[7:0] www.analog.com Analog Devices | 58...
  • Page 59 PCM_DMMIX_CFG[1:0] Source 1[7:0] 0x20 PCM_DMMIX_CH1_SOURCE[3:0] PCM_DMMIX_CH0_SOURCE[3:0] Source 2[7:0] PCM Tx 0x20 Drive – – – – – – PCM_DOUT_DRV[1:0] Strengt h[7:0] PCM Tx 0x20 Source PCM_IMON_ PCM_VMON_E – – – – – – Enables [7:0] www.analog.com Analog Devices | 59...
  • Page 60 – – SPK_AMP_SSM_MOD[1:0] Configu ration[7: Speaker Amplifie 0x20 r Edge – – – – SPK_AMP_FALL_SR[1:0] SPK_AMP_RISE_SR[1:0] Rate Control[ 7:0] Speaker Channel 0x20 Pink SPK_PINK_NOI – – – – – – – Noise SE_EN Enable[ 7:0] www.analog.com Analog Devices | 60...
  • Page 61 Browno 0x20 Protecti – – – – ALC_MAX_ATTEN[3:0] on ALC Attenuat ion[7:0] Browno 0x20 Protecti – – – – – ALC_RLS_DBT[2:0] on ALC Release [7:0] 0x20 ALC_UNMUT ALC_MUTE_ Browno – – ALC_MUTE_DELAY[2:0] ALC_MUTE_EN E_RAMP_EN RAMP_EN www.analog.com Analog Devices | 61...
  • Page 62: 0X20

    – – – – – 7:0] Device and Revision ID Revisio 0x22 REV_ID[7:0] ID[7:0] Register Details Software Reset (0x2000) Field – – – – – – – Reset – – – – – – – www.analog.com Analog Devices | 62...
  • Page 63: Device Status Raw 1[7:0]

    0x0: Power-down transition from active state to software-shutdown state is not done (no transition or transition is in progress). PWRDN_DONE_RAW – Power-down transition done statrus raw bit. 0x1: Power-down transition from active state to software-shutdown state done (transition completed). www.analog.com Analog Devices | 63...
  • Page 64: Pvdd_Uvlo Spk_Ovc_R

    ALC threshold. voltage level recovers (rises above threshold). PVDD undervoltage lockout error raw status PVDD_UVLO_SHDN_RAW – 0x0: PVDD UVLO has not triggered during bit. active-state operation. 0x1: PVDD UVLO has triggered during active-state operation. www.analog.com Analog Devices | 64...
  • Page 65: Otp_Fail_Sta

    CLK_ERR_STATE – Clock monitor error state bit. 0x0: BCLK was present during active-mode operation since the last state clear. 0x1: BCLK was stopped during active-mode operation since the last state clear. www.analog.com Analog Devices | 65...
  • Page 66 PVDD_UVLO_SHDN_STATE – PVDD UVLO error state bit. 0x0: PVDD UVLO was not triggered during normal operation since the last state clear. 0x1: PVDD UVLO was triggered during normal operation since the last state clear. www.analog.com Analog Devices | 66...
  • Page 67: Spk_Clip_Sta

    (and is compared to the measured SPKMON_THRESH output level): Threshold (voltage) = SPKMON_THRESH x 0.02924V If the current sense channel is disabled, the threshold is calculated as % of www.analog.com Analog Devices | 67...
  • Page 68 – – Access Type – – – – Write, Read BITFIELD BITS DESCRIPTION DECODE 0x0: 10ms 0x1: 25ms Sets the time duration over which the SPKMON_DURATION 0x2: 50ms speaker output monitor must consecutively 0x3: 75ms www.analog.com Analog Devices | 68...
  • Page 69 BITS DESCRIPTION DECODE 00: Reserved Configures the PCM data word size for 01: 16-bit PCM_CHANSZ each channel. 10: 24-bit 11: 32-bit 0x0: I S Mode PCM_FORMAT Selects the PCM data format. 0x1: Left-justified 0x2: Reserved www.analog.com Analog Devices | 69...
  • Page 70 0x3: 48 0x4: 64 0x5: 96 Selects the number of BCLKs per LRCLK 0x6: 128 PCM_BSEL expected by the PCM Interface. 0x7: 192 0x8: 256 0x9: 384 0xA: 512 0xB: 320 0xC to 0xF: Reserved www.analog.com Analog Devices | 70...
  • Page 71 Selects the data output (DOUT) slots for the 0x2: Slot 02/03 PCM_VMON_SLOT voltage feedback channel output data. In non- 0x22 to 0x3D: ... TDM mode, only slot 0 and slot 1 are valid. 0x3E: Slot 62/63 0x3F: Reserved www.analog.com Analog Devices | 71...
  • Page 72 PCM Tx HiZ Control 2 (0x2051) Field PCM_TX_SLOT_HIZ[55:48] Reset 0xFF Access Type Write, Read www.analog.com Analog Devices | 72...
  • Page 73 PCM_TX_SLOT_HIZ 1: Output high impedance (Hi-Z) on the output unused, and is disregarded if an output data slot if unused. source is assigned to the slot and the output data source is enabled. www.analog.com Analog Devices | 73...
  • Page 74 PCM Tx HiZ Control 7 (0x2056) Field PCM_TX_SLOT_HIZ[15:8] Reset 0xFF Access Type Write, Read www.analog.com Analog Devices | 74...
  • Page 75 0x0: Output of mono mixer is Channel 0. 0x1: Output of mono mixer is Channel 1. Determines the behavior of the mono mixer 0x2: Output of mono mixer is (Channel 0 PCM_DMMIX_CFG circuit. +Channel1)/2. 0x3: Reserved PCM RX Source 2 (0x2059) www.analog.com Analog Devices | 75...
  • Page 76 DESCRIPTION DECODE Enables transmit of the current sense ADC 0x0: Disable current sense ADC data transmit. PCM_IMON_EN TXEN channel output data on the assigned data 0x1: Enable current sense ADC data transmit. output (DOUT) slot. www.analog.com Analog Devices | 76...
  • Page 77 Enables the data output (DOUT) of the PCM 0x0: PCM T disabled. PCM_TX_EN – 0x1: PCM T enabled. interface. Speaker Channel Volume Control (0x2090) Field – SPK_VOL[6:0] Reset – 0b0000000 Access Type – Write, Read www.analog.com Analog Devices | 77...
  • Page 78 1: DC blocking filter enabled. Speaker Amplifier Output Configuration (0x2092) Field – – – SPK_DAC_MODE SPK_AMP_MODE SPK_GAIN[2:0] Reset – – – 0b011 Access Type – – – Write, Read Write, Read Write, Read www.analog.com Analog Devices | 78...
  • Page 79 The expected PVDD supply range is different based on the SPK_AMP_MODE 0x0: Single-cell mode (default for MAX98388). selected speaker amplifier operating mode. 0x1: Two-cell/boosted mode (default for The MAX98388 defaults to single-cell mode MAX98389).
  • Page 80 Speaker Channel and Amp Enable (0x209F) Field – – – – – – – SPK_EN Reset – – – – – – – Access Type – – – – – – – Write, Read www.analog.com Analog Devices | 80...
  • Page 81 When this bit is set to 1, the current 0x0: Current sense ADC channel is disabled. IVFB_I_EN – 0x1: Current sense ADC channel is enabled. sense ADC channel is powered up when the device is in the active state (EN = 1). www.analog.com Analog Devices | 81...
  • Page 82 0x1: 10µs / dB 0x2: 20µs / dB 0x3: 40µs / dB 0x4: 80µs / dB ALC_ATK_RATE Selects the ALC attack rate. 0x5: 160µs / dB 0x6: 320µs / dB 0x7: 640µs / dB 0x8: 1.28ms / dB www.analog.com Analog Devices | 82...
  • Page 83 ALC_MAX_ATTEN Selects the ALC attack maximum attenuation. 0x8: -8dBFS 0x9: -9dBFS 0xA: -10dBFS 0xB: -11dBFS 0xC: -12dBFS 0xD: -13dBFS 0xE: -14dBFS 0xF: -15dBFS Brownout Protection ALC Release (0x20E3) Field – – – – – ALC_RLS_DBT[2:0] www.analog.com Analog Devices | 83...
  • Page 84 Selects whether or not the ALC can mute 0x0: ALC cannot mute the speaker channel. ALC_MUTE_EN 0x1: ALC can mute the speaker channel. the speaker channel. Brownout Protection ALC Infinite Hold Release (0x20EE) Field – – – – – – – ALC_RLS_TGR www.analog.com Analog Devices | 84...
  • Page 85 0x1: Overcurrent recover is in automatic an OVC fault condition. retry mode. Control whether or not the device 0x0: Thermal shutdown recovery is in THERM_AUTORESTART_EN manual mode. automatically returns to the active state www.analog.com Analog Devices | 85...
  • Page 86 C interface and control registers. 1: Device enabled. Revision ID (0x22FF) Field REV_ID[7:0] Reset 0x41 Access Type Read Only BITFIELD BITS DESCRIPTION DECODE Revision of the device. Updated at every 0x41: Device revision number. REV_ID – device hardware revision. www.analog.com Analog Devices | 86...
  • Page 87 -40°C to +85°C 16 WLP MAX98388EWE+T -40°C to +85°C 16 WLP MAX98389EWE+ -40°C to +85°C 16 WLP MAX98389EWE+T -40°C to +85°C 16 WLP +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. Chip Information PROCESS: BiCMOS www.analog.com Analog Devices | 87...
  • Page 88 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
  • Page 89 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc. MAX98389EVSYS# Other: MAX98389EWE+T...

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