Yaesu FT-480R Instruction Manual page 19

PLL Circuit Configuration
The local signal 132.6900 MHz — 137.6899 MHz
is generated by Q392; (2SKI9TM-GR)VCO-] in the
PLL Loop 1, amplified by buffers Q3o2. (3SK51-03)
and Q3o39 (2SC535A), and passed through BPF
circuit to eliminate spurious radiation. The signal is
then coupled to the Main Unit.
A portion of the signal from the buffer Q3,22 is
amplified by Qs3o23 (3SK51) and applied to the
mixet Q3o24 (SN76514N), where the signal is mixed
with a heterodyne signal of 129 MHz from PLL
Loop 2, and its frequency is divided by program-
mable divider Q3o., (TC9122P). The digital phase
comparator Q3927 (MB8718) compares the phase
of signal from the programmable divider with that
of 40 kHz reference frequency obtained from
crystal oscillator Q3oo7 (TC5082P) (via a 1/4
divider), producing an error-correction DC voltage.
The output DC voltage is passed through an active
lowpass filter consisting of Q3o923 (2SK19TM-Y)and
Q3025 (2SC732TM-BL), and fed to the VCO-1 to
control its oscillation frequency.
In PLL Loop 2, a 64 MHz signal generated by the
VCXO Qaoi1s (2SC1674L) is fed to buffer Q3o16
(2SC535A) and on to doubler Q3929 (2SC710)
before passing to mixer Q3o.4 (SN76514N) in
PLL 1.
A portion of the VCXO signal is taken to buffer
amplifier Q3o17 (3SK73Y) before passing to mixer
Qsoig (SNI6913P), where the signal is mixed with
a 63 MHz signal generated by VCXO Qsoo0
(2SC1674L) and Qsoi9 (2SC535A), resulting in a
600 kHz signal. The 600 kHz signal is amplified by
Q3019 (2SC945Q) and fed to phase comparator
Q3o14 (TC5081P), which compares the phase of
the signal with that of the 600 kHz signal from
PLL Loop 3, producing an error-correction DC
voltage. The DC voltage is passed through a lowpass
filter and fed to the VCXO to control its oscilla-
tion frequency.
In PLL Loop 3, a 60 MHz signal is generated by
VCO-2 Qyoo, (2SKI9TM-GR) and applied through
buffers Q3902 (3SK73Y) and Q3o1, (28C535A) to a
prescaler, Q3o)2/Q3013 (HD10551), which divides its
frequency by 1/100, thus producing a 600 kHz
signal. A portion of the output of Qyoo2 is fed to
mixer Qjoo3 (SNLI6913P), where the signal is
mixed with a 63 MHz signal which is generated by
Q3o00 (2SC1674L), and applied through a program-
divider
to phase
comparator
Q3o06
(TC5081P) which compares the phase of the signal
with
that of 5 kHz signal which is generated by
Qs3o07_ (TCS082P), producing an error-correction
DC voltage. The DC voltage is passed through a
lowpass filter and fed to the VCO-2 Qyoo, to
control its oscillation frequency.
mable
The frequency control signal from the PLL Control
Unit is fed to Serial/Parallel converters Qyo3, -
Qso33 (uPC4094B) and converted into BCD
code to control the dividing ratio of the program-
mable divider and the VCO and VCXO oscillating
frequency in each PLL loop.
When any VCO is unlocked. an unlock signal from
the phase comparater is fed to the unlock control
circuit consisting of Q3o4; (MPSA13) and Qyoa,
(2SA733P), which controls buffer Q3939 (2SC535A)
to mute the output from the PLL oscillator to
prevent spurious radiation.
PLL Control Circuit
In the PLL Control Unit, a 4 bit parallel processing
CPU is used to control the operating frequency,
UP/DOWN scanning, priority channel, or memory
channel selections. The CPU has one input port,
three 1/O ports and four output ports. The CPU
processes input data by means of the main dial or
other control switches in accordance with the
program stored in an ROM for control of the PLL
frequency, indication of the operating frequency,
or memory channels on digital display. The CPU
is also furnished with a function to halt transmis-
sion when any VCO is unlocked, resulting in a
fail-safe system.
For Service Manuals Contact
MAURITRON TECHNICAL SERVICES
8 Cherry Tree Rd, Chinnor
Oxon OX9 4QY
Tel:- 01844-351694 Fax:- 01844-352554
Email:- enquiries@mauritron.co.uk