Quectel FGM842D Hardware Design page 20

Table 8: Pin Definition of SPI
Pin Name Pin No.
GPIO15 16
GPIO14 17
GPIO17 18
GPIO16 21
The following figure shows the SPI connection between the host and the slave:
FGM842D_Hardware_Design
Alternate
I/O
Function
SPI_CS DIO
SPI_CLK DIO
SPI_MISO DIO
SPI_MOSI DIO
Figure 4: SPI Connection (Master Mode)
SPI_CS
SPI_CLK
SPI_MOSI
SPI_MISO
Module
Figure 5: SPI Connection (Slave Mode)
Wi-Fi&Bluetooth Module Series
Description
SPI chip select
SPI clock
SPI master-in slave-out
SPI master-out slave-in
SPI_CS
SPI_CLK
SPI_MOSI
SPI_MISO
SPI (Master)
Comment
In master mode, it is an
output signal;
In slave mode, it is an input
signal.
In master mode, it is an
output signal;
In slave mode, it is an input
signal.
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