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SL-P999
SL-P999
¢ 1C301 (MN6622): Digital signal processing
vo
vo
Division
Division
Digital output signal
Emphasis signal input
F
bad
Spindle motor "ON" signal
Not used (connected to +5V)
(ON at "L")
o " +4 Pt)
Not used (connected to +5V)
Spindle motor drive signal
GND terminal
Not used, open
N
Clock output (16.9344 MHz)
Focus lock signal input
Clock input (16.9344 MHz)
LAGO
Not used, open
Not used (connected to GND)
7
PFLAG
Not used, open
Frequency puil-in clock signal
(88.2kHz)
nn
< — n n uv fo)
nn
LAG6
Not used, open
PLL extract clock input
(4.2336 MHz)
>
=
Not used, open
Not used, open
Power supply (connected to +5V)
on
m-
| ow
z5/
2
Qe}
o
x
n
Q
MCK
Clock output (4.2336
MHz)
EFM signal input (PLL)
Not used, open
EFM signat input (DSL)
RCK
Not used, open
Drop-out signal ("H" at drop-out)
Clock output
Not used, open
DA15/
SRDATA
DA paratiel output (MSB)/serial
data output (MSB FIRST)
N
PLL frequency comparison
signal
x n ?)
Not connected
DA14/
SRDATA
Not used, open
17
Remote control signal input
DA13/
DA parailel output/serial data
Not used (connected to GND)
SCK
output bit clock
LEEP
Not used (connected to GND)
DA12/
WODCK
Not used, open
UBC
Not used, open
DA11/
BCK
Not used, open
BYTCK
Not used, open
2)
a Q mn
bee)
un
2)
a n uv r aso
m
l =e
Sub-code block (Q-data) clock
(75 Hz)
GND terminal
is]
i
Pa Q x
DA parallel output/R/L signal
DA10/R/L
(R at "H")
Sub-code frame (Q-data) clock
(7.35 kHz)
on
a»
Sub-code (Q-data) output
Not used, open
DA7
S 5
© 7)
Q es] QO
Not used, open
Not used (connected to GND)
a
+
Reset signal input (''L"
= Reset)
27
= c
o
Data input (command
load)
Not used,
open
° c i=) oO x
CLK
Data clock input (command clock)
DATA
Data input (command data)
0
16K RAM DATA
MUTE
Muting control input
16K RAM OE signal
Tracking servo "ON" signal
~"N
Hi
7
ie
" >->
o a
16K RAM WE signal
4 Py
°
z
(ON at")
pei
Processing condition
74
| RAMAO
STAT
(CRC, OTC, CLVOK, TT, STOP)
s
5
16K RAM
address
output
84
RAMA10
¢ 1C304 (MN53015PEU): 4DAC gate array
v0
Division
Gain select signal (Lch).
GAINL
High signal (0~
— 42dB): "H"
]
Low signal (less than —42dB): "L".
Sampling hold signal (Lch).
[A sampling: on
At hold: "L"
Output signal of 20 bits (Lch).
SHL
BIT20L
BIT19L
Output signal of 19 bits (Lch).
Output signal of 18 bits (Lch).
Output signal of 17 bits (Lch).
BIT18L
BIT17L
VDD
BIt clock of DOAL data signal.
Bit clock of DOBL data signal.
Word clock of DOBL data signal.
Input data signal to (—) DAC (Lch).
VSS
COAL
COAL
DOAL
=i|o
<
Oo
COBL
oe
5
COBL
DOBL
Gain select signal (Rch).
Hee signal (0~ —42dB): "H"
]
Low signal (less than —42dB): "L"
17
GAINR
Sampling hold signal (Rch).
be sampling: ae
At hold: "L"
IT20R
BIT19R
BIT18R
BIT17R
z (?)
VSS
< ie) o
COAR
27
=
COAR
DOAR
vDD
COBR
COBR
DOBR
v0
Division
Input signal to set NS of serial data
(MDT).
ine ON: "L" ]
NS OFF: "H"
Use to set the LRPL of the mode
setting serial data (MDT) for digital
filter.
Set to "L" to start operation at the
rising edge of LRCI.
Set to "H" to start operation at the
falling edge of LRCI.
Use to select silent or ordinary
degritching.
Set to "H" to activate silent
degritching.
Set to "L" to select ordinary
degritching.
Use to switch in the smali signal
mode at a play signal level of less
than —42dB.
Set to "H" to switch in the S.S.
mode.
Set to "L" to remain out of the S.S.
mode.
Use to switch in the half-wave (non-
zero cross) operation at a play
signal level of less than —42dB.
be : Half-wave operation
"L" : Full-wave operation
]
-
ie
- NTEST1
- NTEST2
a
_
EF
«
H16L18
a
—
1
|
ial
[a
The smail signal mode is switched
in with the delay time selected with
these pins after the play signal
level is reduced to less than
—42dB.
NTEST1
H
NTEST2
H
Delay time
186 msec
|
| 93msec
93msec
2.8ysec (1 sample)
Use to reset all the chip's internal
D-FFs and T-FFs when the chip
requires checkout (active "L").
Use to invert the polarity of input
data, DIL and DIR, to invert overall
system phase ("H" to invert).
This is the input to select the order
of the output data bits.
ie "H" : 16 bits cael
At "L" : 18 bits DAC
Input signal to set the data bits of
the bit shift.
ie "H" :1 bit snl
At "L" : 2 bit shift
Use to invert the polarity of output
data, DOBL and DOBR ("H" to
invert).
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