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Z690 AQUA OC
Write to Read Delay (tWTR_S)
The number of clocks between the last valid write operation and the next read
command to the same internal bank.
Refresh Cycle Time 2 (tRFC2)
The number of clocks from a Refresh command until the first Activate command to
the same rank.
Refresh Cycle Time per Bank (tRFCpb)
The number of clocks from a Refresh command (per bank) until the first Activate
command to the same rank.
RAS to RAS Delay (tRRD_L)
The number of clocks between two rows activated in different banks of the same
rank.
RAS to RAS Delay (tRRD_S)
The number of clocks between two rows activated in different banks of the same
rank.
Read to Precharge (tRTP)
The number of clocks that are inserted between a read command to a row pre-
charge command to the same rank.
Four Activate Window (tFAW)
The time window in which four activates are allowed the same rank.
CAS Write Latency (tCWL)
Configure CAS Write Latency.
Third Timing
tREFI
Configure refresh cycles at an average periodic interval.
tCKE
Configure the period of time the DDR5 initiates a minimum of one refresh
command internally once it enters Self-Refresh mode.
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