Table of Contents
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DRAM Reference Clock
Select Auto for optimized settings.
DRAM Frequency
If [Auto] is selected, the motherboard will detect the memory module(s) inserted
and assign the appropriate frequency automatically.
DRAM Gear Mode
High gear is good for high frequency.
BCLK Frequency
Configure the BCLK Frequency.
Primary Timing
CAS# Latency (tCL)
The time between sending a column address to the memory and the beginning of the data
in response.
RAS# to CAS# Delay and Row Precharge (tRCDtRP)
RAS# to CAS# Delay : The number of clock cycles required between the opening of a row
of memory and accessing columns within it.
Row Precharge: The number of clock cycles required between the issuing of the precharge
command and opening the next row.
RAS# Active Time (tRAS)
The number of clock cycles required between a bank active command and issuing the
precharge command.
Command Rate (CR)
The delay between when a memory chip is selected and when the first active command can
be issued.
Secondary Timing
Write Recovery Time (tWR)
The amount of delay that must elapse after the completion of a valid write operation,
before an active bank can be precharged.
Write to Read Delay (tWTR_L)
The number of clocks between the last valid write operation and the next read
command to the same internal bank.
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