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Table 3. PCIe4 switches in the system.
Features provided
Lanes and ports
Lane and polarity reversal
All ports support concurrent maintenance through I2C
bus.
End-to-end cyclic redundancy check (CRC) and poison
bit error checking
Data path parity
Memory error correction
Advanced error reporting
Aggregate full duplex bandwidth
Designate any port as the upstream port
27x27 mm, 676-pin FCBGA package
Power consumption
Notes:
• Up to three adapters can be in SR-IOV shared mode.
• Of the three adapters in SR-IOV shared mode, a maximum of two adapters can be either FC EC2S or EC2U.
Figure 1 on page 3 shows the rear view of the system with the location codes for the PCIe4 adapter
slots.
Table 4 on page 3 lists the PCIe4 adapter slot locations and details for the 9009-41G, 9009-42G, and
9223-42S systems.
2 Power Systems: Adapter placement for the 9009-41A, 9009-41G, 9009-42A, 9009-42G, 9223-42H, or
9223-42S
Switch 1 and switch 2
52-lane, 12-ports, PCIe4
With integrated 8.0 gigatransfers per second (GT/s)
Serializer/Deserializer (SerDes) speed negotiation for
each port
Supported
Yes
Supported
Supported
Supported
Supported
768 GT/s
Yes
Yes
• Nominal: 8 watts
• Maximum: 12 watts
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