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4. Tuner/CI Block Diagram
TDSQ-
+3.3V_D_Demod
+3.3V_TU
G651D
[+3.3V_S2_DEMOD] 32
[+3.3V_TUNER] 5
[+.1.8V_TUNER] 7
[+1.23V_S2_DEMOD] 30
[S2_F22_OUTPUT] 33
[LNB] 36
[S2_SCL] 34
[S2_SDA] 35
100Ω
[RESET] 2
[SLC] 3
33Ω
[SDA] 4
[ERROR] 16
[SYNC] 17
[VALID] 18
[MCLK] 19
[D0-7] 20-27
[S2_RESET] 31
[CVBS] 8
[SIF] 6
+1.8_TU
+1.23V_D_Demod
+3.3V_NORMAL
3.3K Ω
LNB_TX
LNB_OUT
22 Ω
I2C_SCL4
I2C_SDA4
/TU_RESET1
33 Ω
IC2_SDA6
IC2_SCL6
FE_DEMOD1_TS_ERROR
FE_DEMOD1_TS_SYNC
FE_DEMOD1_TS_VAL
FE_DEMOD1_TS_CLK
FE_DEMOD1_TS_DATA [0-7]
/S2_RESET
CVBS
TUNER_SIF
10 [TONECTRL]
LNB
2 [LNB]
IC6900
7 [SCL]
A8303SESTR-TB
8 [SDA]
LG1154
H32
[CAM_VCCEN_N]
D32[CAM_CD1_N]
AP6 [SCL3]
AR6 [SDA3]
E32[CAM_CD2_N]
G32[CAM_VS1_N]
AG6[GPIO10]
AH34 [SCL5]
F33[CAM_CE1_N]
AH33 [SDA5]
F34[CAM_CE2_N]
H37[EB_BE_N0]
AL37[TP_DVB_ERR]
H36[EB_BE_N1]
AL36 [TP_DVB_SOP]
AL35 [TP_DVB_VAL]
AM36 [TP_DVB_CLK]
[EB_ADDR0-14]
[EB_DATA0-7]
G34[CAM_RESET]
E33[CAM_WAIT]
[TP_DVB_DATA0-7]
D33[CAM_INPACK]
D34[CAM_REG]
F32[CAM_IREQ]
J36[EB_OE]
AM18 [ADIN7_SRV]
H35[EB_WE]
A28[TPI_CLK]
V15[CVBS_IN1]
B28[TPI_VAL]
B29[TPI_SOP]
H18[AAD_ADC_SIF]
TPI_DATA[0-7]
TPO_DATA[0-7]
PCM_5V_CTL
CI 5V
Power detect
+5V_CI_ON
+5V_NORMAL
10K Ω
10K Ω
/CI_CD1
/CI_CD2
CI_VS1
/PCM_CE1
/PCM_CE2
/PCM_IOWR
/PCM_IORD
CI_ADDR[0-14]
CI_A_ADDR[0-14]
CI_DATA[0-7]
CI_A_DATA[0-7]
PCM_RST
/PCM_WAIT
PCM_INPACK
/PCM_REG
/PCM_IRQA
/PCM_OE
/PCM_WE
100 Ω
33 Ω
CI Slot
+5V_CI_ON
VCC
CI_DET1
CI_DET2
VS1
CARD_EN1
CARD_EN2
IOWR
IORD
ADDR[0-14]
DATA[0-7]
CI_RESET
CI_WAIT
INPACK
REG
/IRQA
O_EN
WR_EN
CI_TS_CLK
TS_OUT_CLK
CI_TS_VAL
TS_OUT_VAL
CI_TS_SYNC
TS_OUT_SYNC
CI_TS_DATA[0-7]
CI_IN_TS_DATA[0-7]
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