Table of Contents
Advertisement
System Configuration
Clock for LG1154D
MAIN Clock(24Mhz)
10pF
XIN_MAIN
C100
10pF
XO_MAIN
C101
System Clock for Analog block(24Mhz)
PLL SET[1:0] : internal pull up
"00" : CPU(1200Mhz),M0 / M1 DDR(792,792 Mhz)
"01" : CPU(1056Mhz),M0 / M1 DDR(672,672 Mhz)
"10" : CPU(1056Mhz),M0 / M1 DDR(792,792 Mhz)
"11" : CPU( 960Mhz),M0 / M1 DDR(792,792 Mhz)
OPT
R100
33
PLLSET1
R101
33
PLLSET0
OPT
OP MODE[1:0]
"00" : Normal Mode
"01/10/11" : Internal Test mode
+3.3V_NORMAL
+3.3V_NORMAL
+3.3V_NORMAL
INSTANT boot MODE
BOOT MODE
"1 : Instant boot
"0 : EMMC
"0 : normal
"1 : TEST MODE
(internal pull down)
INSTANT_BOOT
BOOT_MODE
BOOT_MODE0
INSTANT_MODE0
Jtag I/F For Main
TP101
TRST_N0
TP102
TDI0
TDO0
TP103
TP104
TMS0
TCK0
TP105
TP106
SOC_RESET
C106
+3.3V_NORMAL
33pF
50V
TP108
TP109
Model Option
+3.3V_NORMAL
HW_OPT_0
AREA option1
HW_OPT_1
FRC option
HW_OPT_2
Pannel Resol
HW_OPT_3
OLED option
HW_OPT_4
EPI PANEL version
HW_OPT_5
reserved
HW_OPT_6
CP BOX
HW_OPT_7
T2 support
HW_OPT_8
satellite support
HW_OPT_9
AREA option2
HW_OPT_10
EPI selection
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
EEPROM_ST
IC102-*1
NVRAM
M24256-BRMN6TP
+3.3V_NORMAL
E0
1
8
E1
EEPROM_RENESAS
2
7
IC102
C103
E2
0.1uF
3
6
R1EX24256BSAS0A
Write Protection
VSS
4
5
- Low
: Normal Operation
A0
VCC
1
8
- High : Write Protection
A1
WP
2
7
A0'h
A2
SCL
3
6
R139
33
I2C_SCL5
VSS
SDA
4
5
R140
33
I2C_SDA5
OPT
R133
33
OPM1
R134
33
OPM0
OPT
EPHY_INT
M_REMOTE_RX
M_REMOTE_TX
M_REMOTE_RTS
M_REMOTE_CTS
IRB_SPI_SS
TP100
IRB_SPI_SS
TP107
IRB_SPI_MOSI
IRB_SPI_MOSI
TP110
IRB_SPI_MISO
IRB_SPI_MISO
TP111
IRB_SPI_CK
IRB_SPI_CK
HIGH
LOW
MODEL_OPT_0
Area1
Taiwan
non Taiwan
MODEL_OPT_1
FRC
FRC(120Hz)
No FRC(60Hz)
MODEL_OPT_2
Panel
FHD
UD
I2C_SCL_MICOM_SOC
MODEL_OPT_3
OLED
OLED
NON OLED
I2C_SDA_MICOM_SOC
I2C_SCL2_SOC
MODEL_OPT_4
Module
V13
V12
I2C_SDA2_SOC
Reserved
Default
MODEL_OPT_5
CP BOX
Enable
Disable
MODEL_OPT_6
MODEL_OPT_7
T2 Tuner
Support
Not Support
MODEL_OPT_8
S Tuner
Support
Not Support
MODEL_OPT_9
Area2
AJ_JA
non AJ_JA
MODEL_OPT_10
EPI
Support
Not Support
I2C_SDA_MICOM
+3.3V_TU
+3.3V_TU
I2C_SCL_MICOM
+3.3V_NORMAL
+3.3V_NORMAL
I2C PULL UP
VCC
WC
SCL
SDA
A26
XIN_MAIN
XIN
R152
560
B26
XO_MAIN
XOUT
B27
XTAL_BYPASS
AT37
H13DA_XTAL
AU16
SOC_RESET
PORES_N
AD34
OPM1
OPM1
AD33
OPM0
OPM0
AT26
H13A_SCL
H13DA_SCL
AU26
H13A_SDA
H13DA_SDA
AP9
TRST_N0
TRST_N0
AN9
TMS0
TMS0
AP11
TCK0
TCK0
AN11
TDI0
TDI0
AN10
TDO0
TDO0
AM10
TRST_N1
AM9
TMS1
AM11
TCK1
AM12
TDI1
AL11
TDO1
AL9
PLLSET1
PLLSET1
AL10
PLLSET0
PLLSET0
AE34
BOOT_MODE
BOOT_MODE
Y33
R149
33
EXT_INTR3/GPIO70
W32
LG1154D_H13D
EXT_INTR2/GPIO69
W33
R151
33
EXT_INTR1/GPIO68
W34
R174
33
EXT_INTR0/GPIO67
AU12
SOC_RX
UART0_RXD
AT12
SOC_TX
UART0_TXD
AU13
UART1_RXD
AT13
UART1_TXD
AP12
UART1_RTS
AR12
UART1_CTS
AE35
SPI_CS0/GPIO36
AE36
SPI_DO0/GPIO38
AF36
SPI_DI0/GPIO39
AF35
SPI_SCLK0/GPIO37
AG34
SPI_CS1
AF33
SPI_DO1
AG33
SPI_DI1
AG32
SPI_SCLK1
AR15
I2C_SCL1
SCL0/GPIO66
AP15
I2C_SDA1
SDA0/GPIO65
AR16
SCL1/GPIO64
AP16
SDA1/GPIO79
AP17
SCL2/GPIO78
AR17
SDA2/GPIO77
AP6
I2C_SCL4
SCL3
AR6
I2C_SDA4
SDA3
AH32
I2C_SCL5
SCL4
AJ33
I2C_SDA5
SDA4
AH34
I2C_SCL6
SCL5
AH33
I2C_SDA6
SDA5
33
R105
I2C_SDA_MICOM_SOC
33
R106
I2C_SCL_MICOM_SOC
33
R102
I2C_SDA2
I2C_SDA2_SOC
33
R104
I2C_SCL2
I2C_SCL2_SOC
I2C_SDA1
I2C_SCL1
I2C_SDA_MICOM_SOC
I2C_SCL_MICOM_SOC
+3.3V_NORMAL
I2C_SDA2_SOC
I2C_SCL2_SOC
I2C_SDA4
I2C for tuner
I2C_SCL4
I2C_SDA5
I2C_SCL5
I2C_SDA6
I2C for tuner
I2C_SCL6
EB_ADDR[0-14]
EMMC_DATA[0-7]
EB_DATA[0-7]
IC100
AC-coupling CAP
Place near by LG1154D
AL34
GPIO31
CAM_SLIDE_DET
AM33
GPIO30
AM32
GPIO29
AF30
GPIO28
AN34
+3.3V_NORMAL
/RST_PHY
GPIO27
AK34
GPIO26
RF_SWITCH_CTL
AL33
For ISP
GPIO25
AL32
SW100
GPIO24
AR9
JTP-1127WEM
UART2_TX
GPIO23/UART2_TX
AM5
2
1
GPIO22/UART2_RX
UART2_RX
AM6
AMP_RESET_N
GPIO21
AM7
4
3
GPIO20
AL6
GPIO19
INSTANT_BOOT
AK7
DEBUG
GPIO18
AK6
GPIO17
SC_DET
local dimming
AK5
GPIO16
AV1_CVBS_DET
I2C port
AJ5
GPIO15
AJ6
COMP1_DET
GPIO14
AJ7
GPIO13
M_RFModule_RESET
AH6
HP_DET
GPIO12
AG7
GPIO11
FRC_RESET
AG6
/TU_RESET1
GPIO10
AG5
/S2_RESET
GPIO9
AF5
VCOM_DYN
GPIO8
AH30
PMIC_RESET
GPIO7
AG30
GPIO6
/RST_HUB
AN33
GPIO5
FE_LNA_Ctrl2
AK33
GPIO4
/TU_RESET2
AE30
HDMI_S/W_RESET
GPIO3
AD30
GPIO2
AN32
FE_LNA_Ctrl1
GPIO1
AK32
GPIO0
HDMI_INT
+3.3V_NORMAL
AC32
R169
3.3K
DDCD0_CK
AC33
R170
3.3K
DDCD0_DA
AB33
HPD0
AE37
PHY0_ARC_OUT_0
SPDIF_OUT_ARC
AC36
PHY0_RX0N_0
HDMI_RX0-
AC37
PHY0_RX0P_0
HDMI_RX0+
AB36
PHY0_RX1N_0
HDMI_RX1-
AB37
PHY0_RX1P_0
HDMI_RX1+
AA36
PHY0_RX2N_0
HDMI_RX2-
AA37
PHY0_RX2P_0
HDMI_RX2+
AD36
PHY0_RXCN_0
HDMI_CLK-
AD37
PHY0_RXCP_0
HDMI_CLK+
R32
HUB_PORT_OVER0
/USB_OCD1
R33
HUB_VBUS_CTRL0
USB_CTL1
Debug
+3.3V_NORMAL
P101
12507WS-04L
1
DEBUG
2
UART2_RX
3
4
UART2_TX
5
BSD-NC4_H001-HD
2012-11-14
H13 D CHIP
LGE Internal Use Only
Advertisement
Table of Contents
