Attenuator Theory; Acquisition System - HP 54520 Series Service Manual

Attenuator Theory
Attenuator Theory
The channel input signals are conditioned by the attenuator/preamps, thick film hybrids
containing passive attenuators, an impedance converter, and a programmable amplifier. The
channel sensitivity, as displayed, defaults to the standard 1-2-5 sequence (other calibrated
sensitivities can also be set). However, the firmware uses two passive attenuators, 5:1 and
25:1 to get attenuations of 1:1, 5:1, 25:1, and 125:1. With the attenuation and programmable
gain of the amplifier the entire sensitivity range is calibrated. (On ranges below 7 mV/div, the
firmware expands the signal digitally.)
The input has a selectable 1 MQ or 50 Q input impedance. Compensation for the passive
attenuators is laser trimmed and not adjustable. After the passive attenuators, the signal is
split into high-frequency and low-frequency components. Low-frequency components are
amplified on the main assembly where they are combined with the offset voltage. The ac
coupling and low-frequency reject are implemented in the low-frequency amplifier.
The high- and low-frequency components of the signal are recombined and applied to the
input FET of the preamp. The FET provides a high impedance load for the input attenuators
and a low impedance drive for the preamp. The programmable preamp adjusts the gain to suit
the required sensitivity and provides two output signals to the Main assembly. One signal is
the same phase as the input and goes to the trigger circuitry. The other is of opposite phase
and is sent to the ADC hybrid.
Main Assembly Theory
The main assembly includes two major sections. One section is the acquisition system which
conditions, stores, and processes the input signals. The other section is the system control
with a 68020 microprocessor and 68882 coprocessor, ROM and RAM, and other associated
circuitry. The main block diagram has been divided into two sections: acquisition and system
control. The figure on the previous page is the acquisition block diagram and the figure on
page 8-10 is the system control block diagram.
Acquisition System
The acquisition circuitry provides the sampling, digitizing, and storing of the signals from the
channel attenuators. The four channels are identical. The auxiliary trigger input (from the
rear panel) cannot be displayed. The trigger signals synchronize acquisition through the
trigger and time base circuitry. A 100-MHz oscillator and the time base provide the base
sample rates.
ADC Hybrid The ADC hybrid provides all of the sampling, digitizing, and high-speed
waveform storage. The ADC includes a phase-locked loop frequency converter that, for
sample rates from 250 MHz to 2 GHz, multiplies the input clock from the time base.
Trigger There are two main trigger circuits: Analog Trigger and Logic Trigger. Trigger
signals from the channel and the external trigger attenuators are fed to the analog trigger.
The analog trigger circuitry selects dc, ac, low-frequency reject, and noise reject
(hysteresis) modes and sets the trigger levels. The analog trigger circuitry also selects
the trigger for certain trigger modes such as edges and patterns.
The channel triggers and the selected trigger are sent to the Logic Trigger. The logic trigger
provides the complex triggering functions, such as holdoff, delay, and pattern duration and
range, as well as the interface to the time base.
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