Xsys Interface - XMOS XS1-L2 Hardware Manual

USB Audio 2.0 Reference Design, XS1-L2 Edition Hardware Manual (1.6) 14/32

11 XSYS Interface [18]

A standard XMOS XSYS interface is provided to allow host debug of the board via
JTAG.
An XTAG2 USB debug adapter can be plugged into this port to allow running/debug-
ging code, programming the FLASH memory via the XS1-L2 and selection of boot
mode. It is not recommended to use an original (FTDI based) XTAG with the L2
device, as this is not as fast as the XTAG2 and can have signal drive strength issues.
A 20-way IDC header is used as the physical connector and the pinout of this is
shown below:
Signal
TRST_N
TMS
TCK
TD1
TD2
SRST_N
DEBUG
XMOS-LINK 6, 10, 14, 18
GND
NC
As discussed in the Boot section the XS1-L2 MODE2 and MODE3 pins are connected
to the TRST_N signal.
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Pin Description
3 JTAG Test Reset. Active low
7 JTAG Test Mode Select
9 JTAG Test Clock
5 JTAG Test Data. From debug adapter to XS1-L2
13 JTAG Test Data. From XS1-L2 to debug adapter
15 System Reset. Active low. Resets XS1-L2 device
11 XS1-L2 DEBUG Interrupt line
This is a 2-wire XMOS-Link for advanced debug
4, 8, 12, 16, 20 Ground
1, 2, 17, 19 These pins are not connected
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