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EN 34
7.
LC9.3L LA
2
7.6
I
C
Refer to
Figure 7-8
for the I
MT5392
7.7
TCON
The Timing Controller is integrated in the SSB ("Forward
Integration" concept). Refer to
block diagram.
Main Platform
2010-Mar-26
Circuit Descriptions
2
C architecture.
+3V3_SW
SDA-MAIN
OSDA0 (J30)
OSCL0 (J29)
SCL-MAIN
+3V3_SW
AMBI_SDA
OSDA1 (K30)
OSCL1 (K29)
AMBI_SCL
DDC_SDA
OSDA2 (AJ10)
OSCL2 (AK10)
DDC_SCL
+3V3_SW
FRONTEND_SDA
L28
L29
FRONTEND_SCL
Figure 7-8 I
Figure 7-9
for the TCON system
LVDS
(10bit)
Gamma
Reference
Voltage
+3V3
+ 1V2
+12V
Power
Block
TCON
SSB
Figure 7-9 TCON system block diagram
ForDebugging
10K
10K
22R
5
6
22R
10p
10p
100R
48
100R
47
40
27
68
22R
67
47p
TUNER_SDA
1R
100R
1R
100R
TUNER_SCL
2
C architecture
EEPROM
Timing
Controller
Control
Signals
+ 15.6V
VGH (+35V)
VGL ( − 6V)
+3V3_SW
NVM
7605
Ambilight
μController
7801
HDMIMUX
7900
12
TUNER
13
1205
15p
15p
Mini - LVDS
Source Drive IC
TFT – LCD Panel
LCD Panel
18970_207_100325.eps
100325
18920_209_100318.eps
100319
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