Table of Contents
Advertisement
EN 32
7.
LC9.3L LA
V
= +12 V
S
USB2.0
Regulator
5.0 V
+/−0.25 V
7.3
Front-end
Refer to
Figure 7-5
for the front-end architecture.
VA1G5BF8010
RF_SW
GAIN_SW
BB(5 V)
B1(5 V)
AFT
SIF_OUT
VIDEO_OUT
B2(2.5 V)
B3(3.3 V)
B4(1.2 V)
SYRSTN
SDA
SCL
RSEORF
SBYTE
SPBVAL
SRDT
SRCK
Below find an explanation of the signals that are used:
•
RF_SW: switching signal between cable and antenna:
- 0 V: antenna
- 3V3: cable
•
GAIN_SW: Low-Noise Amplifier (LNA)
- "On": antenna
- "Off": cable
•
AFT: Frequency Fine Tuning; for analog use only
•
SIF_OUT: audio for analog channel
•
VIDEO_OUT: video for analog channel
•
SYRSTN: reset for tuner
2010-Mar-26
Circuit Descriptions
Regulator
1.05 V +/−0.05 V
DCDC
1.83 V +/−0.05 V
3.34 V +/−0.16 V
DCDC
5.25 V +/−0.26 V
Regulator
coil
5.20 V
2.50 V
+/−0.26 V
+/−0.12 V
Tuner Circuitry
Figure 7-4 Power architecture
+5 V TUN_DIGITAL
+2V5_SW
+3V3_SW
+1V2_SW
2
I
C
Transport
Figure 7-5 Front-end architecture
8.0 V +/−0.40 V
GDDR3 × 2
Regulator
1.25 V +/-0.06 V
Transistor
Buffer
Stream
•
SDA/SCL: communication between tuner and MT5392
•
SBYTE: transport stream for digital channel inputs
•
SPBVAL: transport stream for digital channel inputs
•
SRDT: transport stream for digital channel inputs
•
SRCK: transport stream for digital channel inputs.
EEPROM
MT5392
NVM
Flash
HDMI MUX
18970_203_100325.eps
GPIO
MT5392
ADIN
Transport
AUDIO IN
stream
MT5392
Input
2
VIDEO IN
I
C
18970_204_100325.eps
100325
100325
Advertisement
Table of Contents
