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7.1.2
SSB Cell Layout
LVDS 51P
MiniLVDS LEFT
D C /D C
a n d
C la s s -D
R
L
7.2
Power Architecture
For an overview of the output voltages of the Power Supplies,
refer to the wiring diagrams in chapter
Refer to
Figure 7-4
for the power architecture.
LVDS 41P
MiniLVDS RIGHT
N AN D F lash
G D D R 3
P b
Y
P r
SVC
SPD IF
O u t p u t
Figure 7-3 SSB cell layout
Block
Diagrams.
Circuit Descriptions
TIMING CONTROLLER
QFP200, 0.5mm
Eth e rn e t
Tra n sce ive r
Eth e rn e t
Q uad -
LVD S
/N AN D
G P IO
I²S
S P D IF
M T5392 U F M J
A udio
D A C
Pit ch :1 .00
m m
A nalog
A udio
Tu n er
C o m p o n e n t
C V B S
V id e o
Y C
R
L
Y
H P
LC9.3L LA
7.
1P81
1M 59
1P80
T C O N D C /D C
NVM
Am bi
LPC2103F
Ser ial T S
AD V3 0 0 2
VG A
A u d io
V G A
EN 31
U SB2.0
18970_209_100326.eps
100326
2010-Mar-26
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