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orkstation 7045A-WT User's Manual
Advanced Chipset Control
Access the submenu to make changes to the following settings.
Warning
: Take caution when changing the Advanced settings. An Incor-
rect value, a very high DRAM frequency or an incorrect DRAM timing may
cause system to become unstable. When this occurs, reset the setting to
the default setting.
SERR Signal Condition
This setting specifi es the ECC Error conditions that an SERR# is to be asserted.
The options are None, Single Bit, Multiple Bit, and Both.
Clock Spectrum Feature
If Enabled, the BIOS will monitor the level of Electromagnetic Interference caused
by the components and will attempt to decrease the interference whenever needed.
The options are Enabled and Disabled.
Intel VT for Directed I/O
Select Enabled to bring up the following Intel VT for Directed I/O (VT-d) Confi guration
submenu. The options are Enabled and Disabled.
VT-d for Port 0 (ESI)/VT-d for Port 1/VT-d for Port 5/VT-d for Port
9/VT-d for DMI Port
Select Enabled to enable VT-d support for the port specifi ed through DRHD
Structures in the ACPI Tables. The options are Disabled and Enabled.
4GB PCI Hole Granularity
This feature allows you to select the granularity of PCI hole for PCI slots. If MTRRs
are not enough, this option may be used to reduce MTRR occupation. The options
are: 256 MB, 512 MB, 1GB and 2GB.
Memory Branch Mode
This option determines how the two memory branches operate. System address
space can either be interleaved between the two branches or Sequential from
one branch to another. Mirror mode allows data correction by maintaining two
copies of data in two branches. Single Channel 0 allows a single DIMM population
during system manufacturing. The options are Interleave, Sequential, Mirroring,
and Single Channel 0.
Branch 0 Rank Sparing/Branch 1 Rank Sparing
Select Enable to enable the function of memory sparing for Memory Bus Branch
0 or Branch 1. The options are Enabled and Disabled.
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