Digital Routing And Clock Generation; Clock Routing - National Instruments PCIe-6323 User Manual

Digital Routing and Clock
Generation
The digital routing circuitry has the following main functions:
• Manages the flow of data between the bus interface and the acquisition/generation
sub-systems (analog input, analog output, digital I/O, and the counters). The digital routing
circuitry uses FIFOs (if present) in each sub-system to ensure efficient data movement.
• Routes timing and control signals. The acquisition/generation sub-systems use these
signals to manage acquisitions and generations. These signals can come from the following
sources:
– Your X Series device
– Other devices in your system through RTSI
– User input through the PFI terminals
– User input through the PXI_STAR terminal
• Routes and generates the main clock signals for the X Series device.

Clock Routing

Figure 9-1 shows the clock routing circuitry of an X Series device.
Onboard
100 MHz
Oscillator
RTSI <0..7>
PXIe_CLK100
PXI_STAR
PFI
PXIe-DSTAR<A, B>
Note (NI PXIe-6386/6396 Devices)
support PXIe_CLK100 and the onboard oscillator. For more information about
special considerations for these devices, go to
Code
smio14ms
Figure 9-1. X Series Clock Routing Circuitry
External
Reference
Clock
PLL
.
10 MHz RefClk
÷ 10
÷
5
÷
PXIe-6386 and PXIe-6396 devices only
ni.com/info
© National Instruments | 9-1
9
(To RTSI <0..7>
Output Selectors)
100 MHz
Timebase
20 MHz
Timebase
100 kHz
200
Timebase
and enter the Info