ASROCK W480D2I User Manual page 48

W480D2I / Z490D2I
ODT WR (A1)
Configure the memory on die termination resistors' WR for channel A1.
ODT WR (B1)
Configure the memory on die termination resistors' WR for channel B1.
ODT NOM (A1)
Use this to change ODT (CH A1) Auto/Manual settings. The default is [Auto].
ODT NOM (B1)
Use this to change ODT (CH B1) Auto/Manual settings. The default is [Auto].
ODT PARK (A1)
Configure the memory on die termination resistors' PARK for channel A1.
ODT PARK (B1)
Configure the memory on die termination resistors' PARK for channel B1
COMP Setting
Dll Bandwidth 0
Configure Dll Bandwidth 0 (1067 MHz) to maximize the performance of
intergrated memory controller.
Dll Bandwidth 1
Configure Dll Bandwidth 1 (1333 MHz) to maximize the performance of intergrated
memory controller.
Dll Bandwidth 2
Configure Dll Bandwidth 2 (1600 MHz) to maximize the performance of
intergrated memory controller.
Dll Bandwidth 3
Configure Dll Bandwidth 3 (1867 MHz) to maximize the performance of intergrated
memory controller.
Advanced Setting
41