Table of Contents
Advertisement
100MHz Slew Rate
Adjust the BCLK signal by defining the maximum change rate of the output voltage.
Higher values will result ina shorter signal rising time.
CPU PLL ORT
Overshoot Reduction Technology improves the BCLK signal to decrease overshoot/
undershoot. Default is Level 3.
PCIE PLL ORT
Overshoot Reduction Technology improves the BCLK signal to decrease overshoot/
undershoot. Default is Level 1.
CPU Output Divider
The default is set to 2 where the max BCLK is 1000 MHz, while divider 4 lowers the
max BCLK to 500 MHz, while divder 10 lowers the max BCLK to 200 MHz, and
divider 1 turns it into 2000 MHz.
SRC0 Source
Choose to select the SRC0 source from CPU PLL or PCIE PLL.
CPU2/SRC1 Source
Choose to select the CPU2/SRC1 source from CPUPLL or PCIE PLL.
BCLK Aware Adaptive Voltage
BCLK Aware Adaptive Voltage enable/disable. When enabled, pcode will be aware
of the BCLK frequency when calculating the CPU V/F curves. This is ideal for
BCLK OC to avoid high voltage overrides.
Boot Performance Mode
Select the performance state that the BIOS will set before OS handoff.
FCLK Frequency
Configure the FCLK Frequency.
Ring to Core Ratio Offset
Disable Ring to Core Ratio Offset so the ring and core can run at the same fre-
quency.
34
Advertisement
Table of Contents
