LG 55UF85 Series Service Manual page 3

IC100
LGE5331(LM15U)
+1.1V_VDDC
L10
VDDC_1 AVDD_NODIE
L11
VDDC_2
L12
VDDC_3
L13
VDDC_4 AVDDL_MHL3_1
L14
VDDC_5 AVDDL_MHL3_2
M10
VDDC_6 AVDD3P3_MHL3_1
M11
VDDC_7 AVDD3P3_MHL3_2
M12
VDDC_8
M13
VDDC_9
M14
VDDC_10 AVDD3P3_ETH
N10
VDDC_11 AVDD3P3_DADC_1
N11
VDDC_12 AVDD3P3_DADC_2
N12
VDDC_13 AVDD3P3_ADC_1
N13
VDDC_14 AVDD3P3_ADC_2
V12
VDDC_15 AVDD3P3_USB_1
V13
VDDC_16 AVDD3P3_USB_2
V14
VDDC_17 AVDD3P3_USB3_1
W12
VDDC_18 AVDD3P3_USB3_2
W13
VDDC_19 AVDD_AU33
W14
VDDC_20 AVDD_EAR33
Y12
VDDC_21 AVDD3P3_DMPLL
Y13
VDDC_22 VDDP_1
Y14
VDDC_23 VDDP_2
AF18
VDDC_24
AF19
VDDC_25
AF20
VDDC_26 AVDD_MOD_1
AG18
VDDC_27 AVDD_MOD_2
AG19
VDDC_28 AVDD_LPLL_1
AG20
VDDC_29 AVDD_LPLL_2
AG21
VDDC_30
AG22
VDDC_31
AH18
VDDC_32 AVDD_PLL_A
AH19
VDDC_33 AVDD_PLL_B
AH20
VDDC_34 AVDD_PLL_C
AH21
VDDC_35
AH22
VDDC_36 VDDP_3318_A_CAP
AVDDL_MOD11
VDDP_3318_C_CAP
W23
AVDDL_PREDRV_1 VDDP_3318_A
Y23
AVDDL_PREDRV_2 VDDP_3318_C
W24
VDDC15_M0 AVDDL_MOD_1
Y24
AVDDL_MOD_2
Y25
AVDD15_MOD_1 AVDD_DDR_A_CMD_1
Y26
AVDD15_MOD_2 AVDD_DDR_A_CMD_2
DVDD_DDR11
AVDD_DDR_A_MCK
AF14
AVDDL_USB3_1 AVDD_DDR_A_DAT_1
AF15
AVDDL_USB3_2 AVDD_DDR_A_DAT_2
+1.1V_VDDC_CPU
AVDD_DDR_A_DAT_3
AA21
VDDC_CPU_1
AVDD_DDR_A_DAT_4
AA27
VDDC_CPU_2 AVDD_DDR_B_CMD_1
AA28
VDDC_CPU_3 AVDD_DDR_B_CMD_2
AA29
VDDC_CPU_4 AVDD_DDR_B_MCK
AB21
VDDC_CPU_5 AVDD_DDR_B_DAT_1
AB22
VDDC_CPU_6 AVDD_DDR_B_DAT_3
AB23
VDDC_CPU_7 AVDD_DDR_B_DAT_4
AB24
VDDC_CPU_8 AVDD_DDR_B_DAT_2
AB25
VDDC_CPU_9 AVDD_DDR_C_CMD_1
AB26
VDDC_CPU_10 AVDD_DDR_C_CMD_2
AB27
VDDC_CPU_11 AVDD_DDR_C_MCK
AB28
VDDC_CPU_12 AVDD_DDR_C_DAT_1
AB29
VDDC_CPU_13 AVDD_DDR_C_DAT_2
AC21
VDDC_CPU_14 AVDD_DDR_C_DAT_3
AC22
VDDC_CPU_15 AVDD_DDR_C_DAT_4
AC23
VDDC_CPU_16
AC24
VDDC_CPU_17 AVDD_DDR_LDO_A
AC25
VDDC_CPU_18 AVDD_DDR_LDO_B
AC26
VDDC_CPU_19 AVDD_DDR_LDO_C
AC27
VDDC_CPU_20
AC28
VDDC_CPU_21
AC29
VDDC_CPU_22 AVDD_HDMI_5V_PA
AC30
VDDC_CPU_23 AVDD_HDMI_5V_PC
AD27
VDDC_CPU_24
AD28
VDDC_CPU_25
AD29
VDDC_CPU_26 GND_EFUSE
AD30
VDDC_CPU_27
DVDD_NODIE
AVDD_DDR_VBP_A_1
N14
DVDD_NODIE AVDD_DDR_VBP_A_2
DVDD_DDR11
R22
DVDD_DDR_1 AVDD_DDR_VBN_A_1
C200
R24
1uF DVDD_DDR_2 AVDD_DDR_VBN_A_2
AF24
25V DVDD_DDR_C
P22
DVDD_DDR_RX_A AVDD_DDR_VBP_B_1
T24
DVDD_DDR_RX_B AVDD_DDR_VBP_B_2
AF25
DVDD_DDR_RX_C
AVDD_DDR_VBN_B_1
AVDD_DDR_VBN_B_2
AVDD_DDR_VBP_C_1
AVDD_DDR_VBP_C_2
AVDD_DDR_VBN_C_1
AVDD_DDR_VBN_C_2
+1.5V_Bypass Cap
+1.5V_DDR VDDC15_M0
L227
PZ1608U121-2R0TF
1st layer
L200
PZ1608U121-2R0TF
2A
C207 C201
10uF 10uF
10V 10V
Close to chip side
Close to chip side
VDDC15_M1
1st layer
L201
PZ1608U121-2R0TF
2A C208 C202
10uF 10uF
10V 10V
Close to chip side Close to chip side
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2015 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
WOL POWER ENABLE CONTROL
AVDD_3P3
+3.5V_ST
V7
DVDD_DDR11
PZ1608U121-2R0TF
T13
AVDD33 L204
T14
L8
+3.3V_NORMAL
M8 C239
0.1uF
AVDD33
W7
WOL_CTL
0 R202
AD7
AD8
Y7
Y8
AL10
AL11
AH14
AVDD_AU33
AH15
AH7
AG7
AL12
AK15
AL15 1st layer
AVDD_PLL33
W26
Y27
Y28
Y29
U18
U19
VDDP_NAND
AL18
L17
L15
G8
Close to chip side
H7
VDDC15_M0
M20
M21
N21
M22
N22
N23
+3.5V_WOL
N24
N25
N26
P25
R25
T25
U25
R26 VDDC15_M1
AE25
AE26
AF26
AE22
AE23
AE24
AF22
VDDC15_M0
VDDC15_M1
N20
P24
AD25
AVDD5V_MHL
U7
P7
P8
VDDC15_M0
L20
0.47uF C210
L21
0.47uF C227
OPT
M24
M25 0.47uF C211
0.47uF C229
OPT
U27
0.47uF C212
V27
0.47uF C230
OPT
U26
V26 0.47uF C213
0.47uF C231 VDDC15_M1
OPT
AD21
0.47uF C214
AD22
0.47uF C234
OPT
AD23
AD24 0.47uF C215
0.47uF C240
OPT
4th layer
C316 C223
10uF 10uF
10V 10V
VDDC15_M1
4th layer
C317 C242
FOR_EMI FOR_EMI FOR_EMI
10uF 10uF
C325 C326 C327
10V 10V
20pF
20pF 20pF
50V 50V 50V
+1.1V_Bypass Cap(CLOSE TO CHIP SIDE)
+1.1V_VDDC
+3.5V_WOL
IC200
AP2151WG-7
IN OUT
5 1
GND
2
R201
1K
EN FLG
OPT
4 3
+1.1V_VDDC
AVDD_3P3
+3.5V_WOL
4th layer
C237
10uF
10V
+1.1V_VDDC_CPU
Close to chip side
IC201
AVDD_3P3
AP2121N-3.3TRE1
VIN VOUT
3 2
1
GND
C206
C205
1uF
0.1uF
10V
16V
5V_HDMI_3 AVDD5V_MHL
R200
10
+3.3V_NORMAL VDDP_NAND
OPT
L222
PZ1608U121-2R0TF
2A
+1.8V
C302
10uF
L223
10V
PZ1608U121-2R0TF
2A
GND JIG POINT
C228
10uF
10V
AVDDL_MOD11
L202
PZ1608U121-2R0TF
2A
C261 C264
10uF 10uF
10V 10V
1st layer
C263
10uF
10V
Close to chip side
+3.3V_Bypass Cap
+3.3V_NORMAL AVDD_PLL33
L215
PZ1608U121-2R0TF
2A
C222
10uF
10V
L203
PZ1608U121-2R0TF
2A
C304
0.1uF
L212
PZ1608U121-2R0TF
2A
DVDD_DDR11
4th layer
L226
PZ1608U121-2R0TF
2A
C271
10uF
10V
Close to chip side
4th layer
Close to chip side
4th layer
C323
10uF
10V
Close to chip side
1st layer 4th layer
C256
10uF
10V
Close to chip side
Close to chip side
AVDD33
4th layer
C217
10uF
10V
Close to chip side
AVDD_AU33
4th layer
C236
10uF
10V
Close to chip side
LM15U 2014-11-26
MAIN2_POWER 2
LGE Internal Use Only