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EFR32 G23 Series
Silicon Laboratories EFR32 G23 Series SoC Manuals
Manuals and User Guides for Silicon Laboratories EFR32 G23 Series SoC. We have
1
Silicon Laboratories EFR32 G23 Series SoC manual available for free PDF download: Reference Manual
Silicon Laboratories EFR32 G23 Series Reference Manual (1251 pages)
Wireless SoC
Brand:
Silicon Laboratories
| Category:
Single board computers
| Size: 13 MB
Table of Contents
Table of Contents
2
TIMER Register Map
22
About this Document
29
Introduction
29
Conventions
30
Related Documentation
31
System Overview
32
Introduction
33
Block Diagrams
34
MCU Features Overview
35
System Processor
37
Introduction
37
Features
38
Functional Description
38
Interrupt Operation
39
Trustzone
39
MSC_IF - Interrupt Flag Register
39
Interrupt Request Lines (IRQ)
40
Memory and Bus System
43
Introduction
43
Functional Description
44
Bus Matrix
45
Flash
46
Sram
46
Peripherals
46
GPIO_PRS0_ASYNCH1ROUTE - ASYNCH1 Port/Pin Select
47
Radio Transceiver
53
Introduction
54
RF Frequency Synthesizer
54
Modulation Modes
55
Transmit Mode
55
Receive Mode
55
Data Buffering
55
Unbuffered Data Transfer
55
Frame Format Support
56
Hardware CRC Support
56
Convolutional Encoding / Decoding
56
Binary Block Encoding / Decoding
56
Data Encryption and Authentication
57
RF Test Modes
57
GPIO_TIMER0_CDTI0ROUTE - CDTI0 Port/Pin Select
57
MSC - Memory System Controller
58
Introduction
58
Features
59
Functional Description
59
Ram Configuration
59
Instruction Cache
60
Device Information (DI) Page
60
User Data (UD)
60
Bootloader
60
Post-Reset Behavior
60
Flash Startup
60
Flash EM0 / EM1 Power down
60
Wait-States
60
Cortex-M33 If-Then Block Folding
61
Line Buffering (Prefetch)
61
Erase and Write Operations
62
DEVINFO - Device Info Page
63
DEVINFO Register Map
64
DEVINFO Register Description
65
Free Running Mode
68
ICACHE - Instruction Cache
94
Cache Operation
95
Performance Measurement
95
ICACHE Register Map
96
ICACHE Register Description
97
Single Descriptor Looped Transfer
97
SYSCFG - System Configuration
103
Ram Retention
103
Ecc
104
Software Interrupts
104
Bus Faults
104
Functional Description
104
SYSCFG Register Map
105
SYSCFG Register Description
108
MPAHBRAM Register Map
125
MPAHBRAM Register Description
126
MSC Register Map
131
MSC Register Description
133
MSC_IPVERSION - IP Version ID
133
MSC_READCTRL - Read Control Register
133
MSC_RDATACTRL - Read Data Control Register
134
MSC_WRITECTRL - Write Control Register
135
MSC_WRITECMD - Write Command Register
136
MSC_ADDRB - Page Erase/Write Address Buffer
137
MSC_WDATA - Write Data Register
137
MSC_STATUS - Status Register
138
MSC_IEN - Interrupt Enable Register
140
MSC_USERDATASIZE - User Data Region Size Register
141
MSC_CMD - Command Register
141
MSC_LOCK - Configuration Lock Register
142
MSC_MISCLOCKWORD - Mass Erase and User Data Page Lock Word
142
MSC_PWRCTRL - Power Control Register
143
MSC_PAGELOCK0 - Main Space Page 0-31 Lock Word
144
MSC_PAGELOCK1 - Main Space Page 32-63 Lock Word
144
DBG - Debug Interface
145
Introduction
145
Features
145
Functional Description
146
Debug Pins
146
Embedded Trace Macrocell V3.5 (ETM)
146
Debug and EM2/EM3
146
CMU - Clock Management Unit
147
Introduction
147
Features
147
Functional Description
148
System Clocks
151
Switching Clock Source
155
RC Oscillator Calibration
157
Energy Modes
160
Clock Output
160
Clock Input from a Pin
161
Clock Output to PRS
161
Interrupts
161
Protection
161
CMU Register Map
162
LESENSE_RESFIFO - Result Fifo
162
CMU Register Description
165
CMU_IPVERSION - IP Version ID
165
CMU_STATUS - Status Register
166
CMU_LOCK - Configuration Lock Register
167
CMU_WDOGLOCK - WDOG Configuration Lock Register
167
CMU_IF - Interrupt Flag Register
168
CMU_IEN - Interrupt Enable Register
168
CMU_CALCMD - Calibration Command Register
169
CMU_CALCTRL - Calibration Control Register
170
CMU_CALCNT - Calibration Result Counter Register
171
CMU_CLKEN0 - Clock Enable Register 0
172
CMU_CLKEN1 - Clock Enable Register 1
174
CMU_SYSCLKCTRL - System Clock Control
176
Lesense_Chx_Evalcfg - Scan Configuration
176
CMU_TRACECLKCTRL - Debug Trace Clock Control
177
CMU_EXPORTCLKCTRL - Export Clock Control
178
CMU_DPLLREFCLKCTRL - Digital PLL Reference Clock Control
180
CMU_EM01GRPACLKCTRL - EM01 Peripheral Group a Clock Control
181
CMU_EM01GRPCCLKCTRL - EM01 Peripheral Group C Clock Control
182
CMU_EM23GRPACLKCTRL - EM23 Peripheral Group a Clock Control
183
CMU_EM4GRPACLKCTRL - EM4 Peripheral Group a Clock Control
183
CMU_IADCCLKCTRL - IADC Clock Control
184
CMU_WDOG0CLKCTRL - Watchdog0 Clock Control
184
CMU_WDOG1CLKCTRL - Watchdog1 Clock Control
185
CMU_EUSART0CLKCTRL - EUSART0 Clock Control
186
CMU_SYSRTC0CLKCTRL - System RTC0 Clock Control
187
CMU_LCDCLKCTRL - LCD Clock Control
187
CMU_VDAC0CLKCTRL - VDAC0 Clock Control
188
CMU_PCNT0CLKCTRL - Pulse Counter 0 Clock Control
189
CMU_RADIOCLKCTRL - Radio Clock Control
189
CMU_LESENSEHFCLKCTRL - LESENSE HF Clock Control
190
Sine Generation Mode
190
Oscillators
191
Introduction
191
HFXO - High Frequency Crystal Oscillator
191
Interrupts and Wakeup
191
Features
192
Functional Description
192
HFXO Register Map
196
VDAC_CFG - Config Register
196
HFXO Register Description
197
VDAC_OUTCTRL - DAC Output Control
210
VDAC_OUTTIMERCFG - DAC out Timer Config Register
211
HFRCO - High-Frequency RC Oscillator
216
Introduction
216
Features
216
Functional Description
216
Input Range and Accuracy Settings
216
Capacitive Sense Mode
217
Output to GPIO
218
ACMP_IPVERSION - IP Version
220
HFRCO Register Map
221
ACMP_EN - ACMP Enable
221
HFRCO Register Description
222
ACMP_INPUTCTRL - Input Control Register
224
DPLL - Digital Phased Locked Loop
226
Introduction
226
Features
226
Functional Description
226
DPLL Register Map
228
DPLL Register Description
229
ACMP_IEN - Interrupt Enable Register
231
LFXO - Low-Frequency Crystal Oscillator
234
Introduction
234
Features
234
Functional Description
234
LFXO Register Map
236
LFXO Register Description
237
Keyscan_Ipversion - Ipversion
237
KEYSCAN_CMD - Command
240
LFRCO - Low-Frequency RC Oscillator
244
Introduction
244
Features
244
Functional Description
244
LFRCO Register Map
246
LFRCO Register Description
247
FSRCO - Fast Start RCO
250
Introduction
250
Features
251
Functional Description
251
FSRCO Register Map
251
FSRCO Register Description
251
ULFRCO - Ultra Low Frequency RC Oscillator
251
Introduction
251
Functional Description
252
SMU - Security Management Unit
253
Introduction
253
Features
253
Functional Description
254
Bus Level Security
254
Privileged Access Control
255
Secure Access Control
255
ARM Trustzone
256
Configuring Managers
256
Configuring Peripherals
256
Configuring Memory
257
Cortex-M33 Integration
257
Exception Handling
258
SMU Lock
258
SMU Register Map
259
SMU Register Description
261
SMU_IPVERSION - IP Version
261
SMU_STATUS - Status Register
262
SMU_LOCK - Lock Register
262
SMU_IF - Interrupt Flag Register
263
SMU_IEN - Interrupt Enable Register
264
SMU_M33CTRL - M33 Control Settings
265
SMU_PPUPATD0 - Privileged Access
266
SMU_PPUPATD1 - Privileged Access
268
SMU_PPUSATD0 - Secure Access
270
SMU_PPUSATD1 - Secure Access
272
SMU_PPUFS - Fault Status
274
SMU_BMPUPATD0 - Privileged Attribute
275
SMU_BMPUSATD0 - Secure Attribute
276
SMU_BMPUFS - Fault Status
277
SMU_BMPUFSADDR - Fault Status Address
277
SMU_ESAURTYPES0 - Region Types 0
278
SMU_ESAURTYPES1 - Region Types 1
278
SMU_ESAUMRB01 - Movable Region Boundary
279
SMU_ESAUMRB12 - Movable Region Boundary
279
SMU_ESAUMRB45 - Movable Region Boundary
280
SMU_ESAUMRB56 - Movable Region Boundary
280
SE - Secure Engine Subsystem
281
Introduction
281
Security Features
281
Security Features Overview
281
Secure Boot with Root of Trust and Secure Loader (RTSL)
282
Secure Debug
282
Cryptographic Accelerator
282
True Random Number Generation
283
SE Mailbox
283
Sending Commands
283
Receiving Responses
283
MAILBOX Register Map
284
MAILBOX Register Description
284
EMU - Energy Management Unit
287
Introduction
287
Features
288
Functional Description
289
Energy Modes
290
Entering Low Energy Modes
294
Exiting a Low Energy Mode
295
Power Domains
296
Voltage Scaling
296
EM0 / EM1 Peripheral Register Retention
297
Power Configurations
297
Buck DC-DC Interface
301
EFP01 Communication
304
Brown out Detector (BOD)
305
Reset Management Unit
306
Temperature Sensor
308
Register Resets
309
Register Locks
309
EMU Register Map
310
EMU Register Description
312
EMU_DECBOD - DECOUPLE LVBOD Control Register
312
EMU_BOD3SENSE - BOD3SENSE Control Register
313
EMU_VREGVDDCMPCTRL - DC-DC VREGVDD Comparator Control Register
313
EMU_PD1PARETCTRL - PD1 Partial Retention Control
314
EMU_IPVERSION - IP Version
314
EMU_LOCK - EMU Configuration Lock Register
315
EMU_IF - Interrupt Flags
316
EMU_IEN - Interrupt Enables
317
EMU_EM4CTRL - EM4 Control
318
EMU_CMD - EMU Command Register
319
EMU_CTRL - EMU Control Register
320
EMU_TEMPLIMITS - EMU Temperature Thresholds
321
EMU_STATUS - EMU Status Register
322
EMU_TEMP - Temperature
323
EMU_RSTCTRL - Reset Management Control Register
324
EMU_RSTCAUSE - Reset Cause
326
EMU_DGIF - Interrupt Flags Debug
327
EMU_DGIEN - Interrupt Enables Debug
328
EMU_EFPIF - EFP Interrupt Register
328
EMU_EFPIEN - EFP Interrupt Enable Register
329
DCDC Register Map
330
DCDC Register Description
331
Dcdc_Ipversion - Ipversion
331
DCDC_CTRL - Control
332
DCDC_EM01CTRL0 - EM01 Control
333
DCDC_EM23CTRL0 - EM23 Control
334
DCDC_PFMXCTRL - PFMX Control Register
335
DCDC_IF - Interrupt Flags
336
DCDC_IEN - Interrupt Enable
337
DCDC_STATUS - Status Register
338
DCDC_SYNCBUSY - Syncbusy Status Register
339
DCDC_LOCK - Lock Register
340
DCDC_LOCKSTATUS - Lock Status Register
340
PRS - Peripheral Reflex System
341
Introduction
341
Features
341
Functional Description
342
Asynchronous Channel Functions
342
Configurable Logic
343
Producers
344
Consumers
351
PRS Register Map
352
PRS Register Description
368
Prs_Ipversion - Prs Ipversion
368
PRS_ASYNC_SWPULSE - Software Pulse Register
369
PRS_ASYNC_SWLEVEL - Software Level Register
370
PRS_ASYNC_PEEK - Async Channel Values
371
PRS_SYNC_PEEK - Sync Channel Values
372
Prs_Async_Chx_Ctrl - Async Channel Control Register
373
Prs_Sync_Chx_Ctrl - Sync Channel Control Register
374
PRS_CONSUMER_CMU_CALDN - CALDN Consumer Register
375
PRS_CONSUMER_CMU_CALUP - CALUP Consumer Register
375
PRS_CONSUMER_EUSART0_CLK - CLK Consumer Register
376
PRS_CONSUMER_EUSART0_RX - RX Consumer Register
376
PRS_CONSUMER_EUSART0_TRIGGER - TRIGGER Consumer Register
377
PRS_CONSUMER_EUSART1_CLK - CLK Consumer Register
377
PRS_CONSUMER_EUSART1_RX - RX Consumer Register
378
PRS_CONSUMER_EUSART1_TRIGGER - TRIGGER Consumer Register
378
PRS_CONSUMER_EUSART2_CLK - CLK Consumer Register
379
PRS_CONSUMER_EUSART2_RX - RX Consumer Register
379
PRS_CONSUMER_EUSART2_TRIGGER - TRIGGER Consumer Register
380
PRS_CONSUMER_IADC0_SCANTRIGGER - SCAN Consumer Register
380
PRS_CONSUMER_IADC0_SINGLETRIGGER - SINGLE Consumer Register
381
PRS_CONSUMER_LDMAXBAR_DMAREQ0 - DMAREQ0 Consumer Register
381
PRS_CONSUMER_LDMAXBAR_DMAREQ1 - DMAREQ1 Consumer Register
382
PRS_CONSUMER_LESENSE_START - START Consumer Register
382
PRS_CONSUMER_LETIMER0_CLEAR - CLEAR Consumer Register
383
PRS_CONSUMER_LETIMER0_START - START Consumer Register
383
PRS_CONSUMER_LETIMER0_STOP - STOP Consumer Register
384
PRS_CONSUMER_MODEM_DIN - MODEM DIN Consumer Register
384
PRS_CONSUMER_PCNT0_S0IN - S0IN Consumer Register
385
PRS_CONSUMER_PCNT0_S1IN - S1IN Consumer Register
385
PRS_CONSUMER_RAC_CLR - CLR Consumer Register
386
PRS_CONSUMER_RAC_CTIIN0 - CTI Consumer Register
386
PRS_CONSUMER_RAC_CTIIN1 - CTI Consumer Register
387
PRS_CONSUMER_RAC_CTIIN2 - CTI Consumer Register
387
PRS_CONSUMER_RAC_CTIIN3 - CTI Consumer Register
388
PRS_CONSUMER_RAC_FORCETX - FORCETX Consumer Register
388
PRS_CONSUMER_RAC_RXDIS - RXDIS Consumer Register
389
PRS_CONSUMER_RAC_RXEN - RXEN Consumer Register
389
PRS_CONSUMER_RAC_TXEN - TXEN Consumer Register
390
PRS_CONSUMER_SETAMPER_TAMPERSRC25 - TAMPERSRC25 Consumer Register
390
PRS_CONSUMER_SETAMPER_TAMPERSRC26 - TAMPERSRC26 Consumer Register
391
PRS_CONSUMER_SETAMPER_TAMPERSRC27 - TAMPERSRC27 Consumer Register
391
PRS_CONSUMER_SETAMPER_TAMPERSRC28 - TAMPERSRC28 Consumer Register
392
PRS_CONSUMER_SETAMPER_TAMPERSRC29 - TAMPERSRC29 Consumer Register
392
PRS_CONSUMER_SETAMPER_TAMPERSRC30 - TAMPERSRC30 Consumer Register
393
PRS_CONSUMER_SETAMPER_TAMPERSRC31 - TAMPERSRC31 Consumer Register
393
PRS_CONSUMER_SYSRTC0_IN0 - IN0 Consumer Register
394
PRS_CONSUMER_SYSRTC0_IN1 - IN1 Consumer Register
394
PRS_CONSUMER_HFXO0_OSCREQ - OSCREQ Consumer Register
395
PRS_CONSUMER_HFXO0_TIMEOUT - TIMEOUT Consumer Register
395
PRS_CONSUMER_CORE_CTIIN0 - CTI0 Consumer Selection
396
PRS_CONSUMER_CORE_CTIIN1 - CTI1 Consumer Selection
396
PRS_CONSUMER_CORE_CTIIN2 - CTI2 Consumer Selection
397
PRS_CONSUMER_CORE_CTIIN3 - CTI3 Consumer Selection
397
PRS_CONSUMER_CORE_M33RXEV - M33 Consumer Selection
398
PRS_CONSUMER_TIMER0_CC0 - CC0 Consumer Register
398
PRS_CONSUMER_TIMER0_CC1 - CC1 Consumer Register
399
PRS_CONSUMER_TIMER0_CC2 - CC2 Consumer Register
399
PRS_CONSUMER_TIMER0_DTI - DTI Consumer Register
400
PRS_CONSUMER_TIMER0_DTIFS1 - DTI Consumer Register
400
PRS_CONSUMER_TIMER0_DTIFS2 - DTI Consumer Register
401
PRS_CONSUMER_TIMER1_CC0 - CC0 Consumer Register
401
PRS_CONSUMER_TIMER1_CC1 - CC1 Consumer Register
402
PRS_CONSUMER_TIMER1_CC2 - CC2 Consumer Register
402
PRS_CONSUMER_TIMER1_DTI - DTI Consumer Register
403
PRS_CONSUMER_TIMER1_DTIFS1 - DTI Consumer Register
403
PRS_CONSUMER_TIMER1_DTIFS2 - DTI Consumer Register
404
PRS_CONSUMER_TIMER2_CC0 - CC0 Consumer Register
404
PRS_CONSUMER_TIMER2_CC1 - CC1 Consumer Register
405
PRS_CONSUMER_TIMER2_CC2 - CC2 Consumer Register
405
PRS_CONSUMER_TIMER2_DTI - DTI Consumer Register
406
PRS_CONSUMER_TIMER2_DTIFS1 - DTI Consumer Register
406
PRS_CONSUMER_TIMER2_DTIFS2 - DTI Consumer Register
407
PRS_CONSUMER_TIMER3_CC0 - CC0 Consumer Register
407
PRS_CONSUMER_TIMER3_CC1 - CC1 Consumer Register
408
PRS_CONSUMER_TIMER3_CC2 - CC2 Consumer Register
408
PRS_CONSUMER_TIMER3_DTI - DTI Consumer Register
409
PRS_CONSUMER_TIMER3_DTIFS1 - DTI Consumer Register
409
PRS_CONSUMER_TIMER3_DTIFS2 - DTI Consumer Register
410
PRS_CONSUMER_TIMER4_CC0 - CC0 Consumer Register
410
PRS_CONSUMER_TIMER4_CC1 - CC1 Consumer Register
411
PRS_CONSUMER_TIMER4_CC2 - CC2 Consumer Register
411
PRS_CONSUMER_TIMER4_DTI - DTI Consumer Register
412
PRS_CONSUMER_TIMER4_DTIFS1 - DTI Consumer Register
412
PRS_CONSUMER_TIMER4_DTIFS2 - DTI Consumer Register
413
PRS_CONSUMER_USART0_CLK - CLK Consumer Register
413
PRS_CONSUMER_USART0_IR - IR Consumer Register
414
PRS_CONSUMER_USART0_RX - RX Consumer Register
414
PRS_CONSUMER_USART0_TRIGGER - TRIGGER Consumer Register
415
PRS_CONSUMER_VDAC0_ASYNCTRIGCH0 - ASYNCTRIG Consumer Register
415
PRS_CONSUMER_VDAC0_ASYNCTRIGCH1 - ASYNCTRIG Consumer Register
416
PRS_CONSUMER_VDAC0_SYNCTRIGCH0 - SYNCTRIG Consumer Register
416
PRS_CONSUMER_VDAC0_SYNCTRIGCH1 - SYNCTRIG Consumer Register
417
PRS_CONSUMER_WDOG0_SRC0 - SRC0 Consumer Register
417
PRS_CONSUMER_WDOG0_SRC1 - SRC1 Consumer Register
418
PRS_CONSUMER_WDOG1_SRC0 - SRC0 Consumer Register
418
PRS_CONSUMER_WDOG1_SRC1 - SRC1 Consumer Register
419
GPCRC - General Purpose Cyclic Redundancy Check
420
Introduction
420
Features
420
Functional Description
421
Polynomial Specification
422
Input and Output Specification
422
Initialization
422
DMA Usage
422
Byte-Level Bit Reversal and Byte Reordering
423
GPCRC Register Map
426
GPCRC Register Description
427
GPCRC_IPVERSION - IP Version ID
427
GPCRC_EN - CRC Enable
428
GPCRC_CTRL - Control Register
429
GPCRC_CMD - Command Register
430
GPCRC_INIT - CRC Init Value
430
GPCRC_POLY - CRC Polynomial Value
431
GPCRC_INPUTDATA - Input 32-Bit Data Register
431
GPCRC_INPUTDATAHWORD - Input 16-Bit Data Register
432
GPCRC_INPUTDATABYTE - Input 8-Bit Data Register
432
GPCRC_DATA - CRC Data Register
433
GPCRC_DATAREV - CRC Data Reverse Register
433
GPCRC_DATABYTEREV - CRC Data Byte Reverse Register
434
SYSRTC - System RTC
435
Introduction
435
Features
436
Functional Description
436
Interrupts and Wake Events
436
Counter
436
Compare Events
436
Capture Events
437
SYSRTC Behavior on Swrst/Disablement/Stop
437
Debug Functionality
437
SYSRTC Register Map
438
SYSRTC Register Description
440
Sysrtc_Ipversion - Ip Version
440
SYSRTC_EN - Module Enable Register
440
SYSRTC_SWRST - Software Reset Register
441
SYSRTC_CFG - Configuration Register
441
SYSRTC_CMD - Command Register
442
SYSRTC_STATUS - Status Register
442
SYSRTC_CNT - Counter Value Register
443
SYSRTC_SYNCBUSY - Synchronization Busy Register
443
SYSRTC_LOCK - Configuration Lock Register
444
SYSRTC_GRP0_IF - Group Interrupt Flags
444
SYSRTC_GRP0_IEN - Group Interrupt Enables
445
SYSRTC_GRP0_CTRL - Group Control Register
446
SYSRTC_GRP0_CMP0VALUE - Compare 0 Value Register
447
SYSRTC_GRP0_CMP1VALUE - Compare 1 Value Register
447
SYSRTC_GRP0_CAP0VALUE - Capture 0 Value Register
448
SYSRTC_GRP0_SYNCBUSY - Synchronization Busy Register
448
BURTC - Back-Up Real Time Counter
449
Introduction
449
Features
449
Functional Description
450
Clock Selection
450
Configuration
450
Debug Features and Description
450
Counter
451
Compare Channel
452
Interrupts
452
Register Lock
452
BURTC Register Map
453
BURTC Register Description
454
BURTC_IPVERSION - IP Version ID
454
BURTC_EN - Module Enable Register
455
BURTC_CFG - Configuration Register
456
BURTC_CMD - Command Register
457
BURTC_STATUS - Status Register
458
BURTC_IF - Interrupt Flag Register
458
BURTC_IEN - Interrupt Enable Register
459
BURTC_PRECNT - Pre-Counter Value Register
459
BURTC_CNT - Counter Value Register
460
BURTC_EM4WUEN - EM4 Wakeup Request Enable Register
460
BURTC_SYNCBUSY - Synchronization Busy Register
461
BURTC_LOCK - Configuration Lock Register
462
BURTC_COMP - Compare Value Register
462
BURAM - Backup RAM
463
Introduction
463
Functional Description
463
BURAM Register Map
463
BURAM Register Description
464
Buram_Retx_Reg - Retention Register
464
LETIMER - Low Energy Timer
465
Introduction
465
Features
465
Functional Description
466
Internal Overview
467
One-Shot Mode
469
Buffered Mode
470
Double Mode
471
Clock Frequency
472
PRS Input Triggers
473
Debug
473
Output Action
474
PRS Output
474
Interrupts
474
Using the LETIMER in EM3
474
Register Access
474
Programmer's Model
475
Free Running Mode
475
One Shot Mode
476
DOUBLE Mode
476
BUFFERED Mode
477
Continuous Output Generation
478
PWM Output
479
LETIMER Register Map
480
LETIMER Register Description
482
LETIMER_IPVERSION - IP Version
482
LETIMER_EN - Module en
482
LETIMER_SWRST - Software Reset Register
483
LETIMER_CTRL - Control Register
484
LETIMER_CMD - Command Register
486
LETIMER_STATUS - Status Register
487
LETIMER_CNT - Counter Value Register
487
LETIMER_COMP0 - Compare Value Register
488
LETIMER_COMP1 - Compare Value Register
488
LETIMER_TOP - Counter TOP Value Register
489
LETIMER_TOPBUFF - Buffered Counter TOP Value
489
LETIMER_REP0 - Repeat Counter Register 0
490
LETIMER_REP1 - Repeat Counter Register 1
490
LETIMER_IF - Interrupt Flag Register
491
LETIMER_IEN - Interrupt Enable Register
492
LETIMER_LOCK - Configuration Lock Register
493
LETIMER_SYNCBUSY - Synchronization Busy Register
494
LETIMER_PRSMODE - PRS Input Mode Select Register
495
TIMER - Timer/Counter
497
Introduction
497
Features
498
Functional Description
499
Register Access
499
Counter Modes
500
Compare/Capture Channels
506
Dead-Time Insertion Unit
517
Debug Mode
521
Interrupts, DMA and PRS Output
521
GPIO Input/Output
521
TIMER Register Description
525
TIMER_IPVERSION - IP Version ID
525
TIMER_CFG - Configuration Register
526
TIMER_CTRL - Control Register
529
TIMER_CMD - Command Register
530
TIMER_STATUS - Status Register
531
TIMER_IF - Interrupt Flag Register
534
TIMER_IEN - Interrupt Enable Register
536
TIMER_TOP - Counter Top Value Register
537
TIMER_TOPB - Counter Top Value Buffer Register
537
TIMER_CNT - Counter Value Register
538
TIMER_LOCK - TIMER Configuration Lock Register
538
TIMER_EN - Module
539
Timer_Ccx_Cfg - CC Channel Configuration Register
540
Timer_Ccx_Ctrl - CC Channel Control Register
542
Timer_Ccx_Oc - OC Channel Value Register
543
Timer_Ccx_Ocb - OC Channel Value Buffer Register
544
Timer_Ccx_Icf - IC Channel Value Register
544
Timer_Ccx_Icof - IC Channel Value Overflow Register
544
TIMER_DTCFG - DTI Configuration Register
545
TIMER_DTTIMECFG - DTI Time Configuration Register
546
TIMER_DTFCFG - DTI Fault Configuration Register
547
TIMER_DTCTRL - DTI Control Register
548
TIMER_DTOGEN - DTI Output Generation Enable Register
549
TIMER_DTFAULT - DTI Fault Register
550
TIMER_DTFAULTC - DTI Fault Clear Register
551
TIMER_DTLOCK - DTI Configuration Lock Register
552
USART - Universal Synchronous Asynchronous Receiver/Transmitter
553
Introduction
553
Features
554
Functional Description
555
Modes of Operation
556
Asynchronous Operation
556
Synchronous Operation
572
Hardware Flow Control
578
Debug Halt
578
PRS-Triggered Transmissions
578
PRS RX Input
578
PRS CLK Input
579
DMA Support
579
Timer
580
Interrupts
585
Irda Modulator/ Demodulator
586
USART Register Map
587
USART Register Description
590
Usart_Ipversion - Ipversion
590
USART_EN - USART Enable
590
USART_CTRL - Control Register
591
USART_FRAME - USART Frame Format Register
596
USART_TRIGCTRL - USART Trigger Control Register
598
USART_CMD - Command Register
599
USART_STATUS - USART Status Register
601
USART_CLKDIV - Clock Control Register
602
USART_RXDATAX - RX Buffer Data Extended Register
603
USART_RXDATA - RX Buffer Data Register
603
USART_RXDOUBLEX - RX Buffer Double Data Extended Register
604
USART_RXDOUBLE - RX FIFO Double Data Register
605
USART_RXDATAXP - RX Buffer Data Extended Peek Register
605
USART_RXDOUBLEXP - RX Buffer Double Data Extended Peek R
606
USART_TXDATAX - TX Buffer Data Extended Register
607
USART_TXDATA - TX Buffer Data Register
608
USART_TXDOUBLEX - TX Buffer Double Data Extended Register
609
USART_TXDOUBLE - TX Buffer Double Data Register
610
USART_IF - Interrupt Flag Register
611
USART_IEN - Interrupt Enable Register
613
USART_IRCTRL - Irda Control Register
614
USART_I2SCTRL - I2S Control Register
615
USART_TIMING - Timing Register
617
USART_CTRLX - Control Register Extended
619
USART_TIMECMP0 - Timer Compare 0
621
USART_TIMECMP1 - Timer Compare 1
623
USART_TIMECMP2 - Timer Compare 2
625
EUSART - Universal Synchronous Asynchronous Receiver/Transmitter
627
Introduction
627
Features
628
Functional Description
629
Modes of Operation
630
Asynchronous Operation
630
Debug Halt
646
Synchronous Operation
650
PRS-Triggered Transmissions
653
PRS RX Input
654
PRS CLK Input
654
DMA Support
654
EUSART Register Map
655
EUSART Register Description
657
EUSART_IPVERSION - IP Version ID
657
EUSART_EN - Enable Register
658
EUSART_CFG0 - Configuration 0 Register
659
EUSART_CFG1 - Configuration 1 Register
662
EUSART_CFG2 - Configuration 2 Register
667
EUSART_FRAMECFG - Frame Format Register
669
EUSART_DTXDATCFG - Default TX DATA Register
670
EUSART_IRHFCFG - HF Irda Mod Config Register
671
EUSART_IRLFCFG - LF Irda Pulse Config Register
672
EUSART_TIMINGCFG - Timing Register
673
EUSART_STARTFRAMECFG - Start Frame Register
675
EUSART_SIGFRAMECFG - Signal Frame Register
675
EUSART_CLKDIV - Clock Divider Register
676
EUSART_TRIGCTRL - Trigger Control Register
676
EUSART_CMD - Command Register
677
EUSART_RXDATA - RX Data Register
678
EUSART_RXDATAP - RX Data Peek Register
678
EUSART_TXDATA - TX Data Register
679
EUSART_STATUS - Status Register
680
EUSART_IF - Interrupt Flag Register
682
EUSART_IEN - Interrupt Enable Register
684
EUSART_SYNCBUSY - Synchronization Busy Register
686
I2C - Inter-Integrated Circuit Interface
688
Introduction
688
Features
688
Functional Description
689
I2C-Bus Overview
690
Enable and Reset
694
Pin Configuration
694
Safely Disabling and Changing Follower Configuration
694
Clock Generation
695
Arbitration
695
Buffers
695
Leader Operation
698
Bus States
706
Follower Operation
706
Transfer Automation
710
Using 10-Bit Addresses
711
Error Handling
711
DMA Support
713
Interrupts
713
Wake-Up
713
I2C Register Map
714
I2C Register Description
716
I2C_IPVERSION - IP VERSION Register
716
I2C_EN - Enable Register
716
I2C_CTRL - Control Register
717
I2C_CMD - Command Register
721
I2C_STATE - State Register
722
I2C_STATUS - Status Register
723
I2C_CLKDIV - Clock Division Register
724
I2C_SADDR - Follower Address Register
724
I2C_SADDRMASK - Follower Address Mask Register
725
I2C_RXDATA - Receive Buffer Data Register
725
I2C_RXDOUBLE - Receive Buffer Double Data Register
726
I2C_RXDATAP - Receive Buffer Data Peek Register
726
I2C_RXDOUBLEP - Receive Buffer Double Data Peek Register
727
I2C_TXDATA - Transmit Buffer Data Register
727
I2C_TXDOUBLE - Transmit Buffer Double Data Register
728
I2C_IF - Interrupt Flag Register
729
I2C_IEN - Interrupt Enable Register
731
IADC - Incremental Analog to Digital Converter
733
Introduction
733
Features
734
Functional Description
735
Register Access
736
Clocking
737
Conversion Timing
738
Reference Selection and Analog Gain
745
Input and Configuration Selection
746
Gain and Offset Correction
751
Output Data Fifos
755
Window Compare
758
Interrupts
759
LESENSE Interface
759
IADC Register Map
760
IADC Register Description
763
Iadc_Ipversion - Ipversion
763
IADC_EN - Enable
763
IADC_CTRL - Control
764
IADC_CMD - Command
766
IADC_TIMER - Timer
767
IADC_STATUS - Status
768
IADC_MASKREQ - Mask Request
769
IADC_STMASK - Scan Table Mask
770
IADC_CMPTHR - Digital Window Comparator Threshold
770
IADC_IF - Interrupt Flags
771
IADC_IEN - Interrupt Enable
773
IADC_TRIGGER - Trigger
775
Iadc_Cfgx - Configuration
778
Iadc_Scalex - Scaling
780
Iadc_Schedx - Scheduling
780
IADC_SINGLEFIFOCFG - Single FIFO Configuration
781
IADC_SINGLEFIFODATA - Single FIFO DATA
782
IADC_SINGLEFIFOSTAT - Single FIFO Status
783
IADC_SINGLEDATA - Single Data
783
IADC_SCANFIFOCFG - Scan FIFO Configuration
784
IADC_SCANFIFODATA - Scan FIFO Read Data
785
IADC_SCANFIFOSTAT - Scan FIFO Status
786
IADC_SCANDATA - Scan Data
786
IADC_SINGLE - Single Queue Port Selection
787
Iadc_Scanx - SCAN Entry
789
GPIO - General Purpose Input/Output
791
Introduction
791
Features
792
Functional Description
793
Pin Configuration
794
Alternate Port Control
796
Slew Rate
796
Input Disable
796
Configuration Lock
796
EM2 Functionality
796
EM4 Functionality
796
EM4 Wakeup
797
Debug Connections
797
Interrupt Generation
798
Output to PRS
799
Peripheral Resource Routing
799
Synchronization
807
GPIO Register Map
808
GPIO Register Description
836
GPIO_IPVERSION - Main
836
GPIO_PORTA_CTRL - Port Control
837
GPIO_PORTA_MODEL - Mode Low
838
GPIO_PORTA_MODEH - Mode High
843
GPIO_PORTA_DOUT - Data out
845
GPIO_PORTA_DIN - Data in
845
GPIO_PORTB_CTRL - Port Control
846
GPIO_PORTB_MODEL - Mode Low
847
GPIO_PORTB_DOUT - Data out
851
GPIO_PORTB_DIN - Data in
851
GPIO_PORTC_CTRL - Port Control
852
GPIO_PORTC_MODEL - Mode Low
853
GPIO_PORTC_MODEH - Mode High
858
GPIO_PORTC_DOUT - Data out
859
GPIO_PORTC_DIN - Data in
860
GPIO_PORTD_CTRL - Port Control
861
GPIO_PORTD_MODEL - Mode Low
862
GPIO_PORTD_DOUT - Data out
865
GPIO_PORTD_DIN - Data in
866
GPIO_LOCK - Lock Register
866
GPIO_GPIOLOCKSTATUS - Lock Status
867
GPIO_ABUSALLOC - a Bus Allocation
868
GPIO_BBUSALLOC - B Bus Allocation
870
GPIO_CDBUSALLOC - CD Bus Allocation
872
GPIO_EXTIPSELL - External Interrupt Port Select Low
874
GPIO_EXTIPSELH - External Interrupt Port Select High
877
GPIO_EXTIPINSELL - External Interrupt Pin Select Low
879
GPIO_EXTIPINSELH - External Interrupt Pin Select High
882
GPIO_EXTIRISE - External Interrupt Rising Edge Trigger
883
GPIO_EXTIFALL - External Interrupt Falling Edge Trigger
884
GPIO_IF - Interrupt Flag
885
GPIO_IEN - Interrupt Enable
887
GPIO_EM4WUEN - EM4 Wakeup Enable
889
GPIO_EM4WUPOL - EM4 Wakeup Polarity
889
GPIO_DBGROUTEPEN - Debugger Route Pin Enable
890
GPIO_TRACEROUTEPEN - Trace Route Pin Enable
891
GPIO_LCDSEG - LCD Segment Enable
892
GPIO_LCDCOM - LCD Common Enable
892
GPIO_ACMP0_ROUTEEN - ACMP0 Pin Enable
893
GPIO_ACMP0_ACMPOUTROUTE - ACMPOUT Port/Pin Select
893
GPIO_ACMP1_ROUTEEN - ACMP1 Pin Enable
894
GPIO_ACMP1_ACMPOUTROUTE - ACMPOUT Port/Pin Select
894
GPIO_CMU_ROUTEEN - CMU Pin Enable
895
GPIO_CMU_CLKIN0ROUTE - CLKIN0 Port/Pin Select
895
GPIO_CMU_CLKOUT0ROUTE - CLKOUT0 Port/Pin Select
896
GPIO_CMU_CLKOUT1ROUTE - CLKOUT1 Port/Pin Select
896
GPIO_CMU_CLKOUT2ROUTE - CLKOUT2 Port/Pin Select
897
GPIO_EUSART0_ROUTEEN - EUSART0 Pin Enable
898
GPIO_EUSART0_CSROUTE - CS Port/Pin Select
899
GPIO_EUSART0_CTSROUTE - CTS Port/Pin Select
899
GPIO_EUSART0_RTSROUTE - RTS Port/Pin Select
900
GPIO_EUSART0_RXROUTE - RX Port/Pin Select
900
GPIO_EUSART0_SCLKROUTE - SCLK Port/Pin Select
901
GPIO_EUSART0_TXROUTE - TX Port/Pin Select
901
GPIO_EUSART1_ROUTEEN - EUSART1 Pin Enable
902
GPIO_EUSART1_CSROUTE - CS Port/Pin Select
903
GPIO_EUSART1_CTSROUTE - CTS Port/Pin Select
903
GPIO_EUSART1_RTSROUTE - RTS Port/Pin Select
904
GPIO_EUSART1_RXROUTE - RX Port/Pin Select
904
GPIO_EUSART1_SCLKROUTE - SCLK Port/Pin Select
905
GPIO_EUSART1_TXROUTE - TX Port/Pin Select
905
GPIO_EUSART2_ROUTEEN - EUSART2 Pin Enable
906
GPIO_EUSART2_CSROUTE - CS Port/Pin Select
907
GPIO_EUSART2_CTSROUTE - CTS Port/Pin Select
907
GPIO_EUSART2_RTSROUTE - RTS Port/Pin Select
908
GPIO_EUSART2_RXROUTE - RX Port/Pin Select
908
GPIO_EUSART2_SCLKROUTE - SCLK Port/Pin Select
909
GPIO_EUSART2_TXROUTE - TX Port/Pin Select
909
GPIO_FRC_ROUTEEN - FRC Pin Enable
910
GPIO_FRC_DCLKROUTE - DCLK Port/Pin Select
910
GPIO_FRC_DFRAMEROUTE - DFRAME Port/Pin Select
911
GPIO_FRC_DOUTROUTE - DOUT Port/Pin Select
911
GPIO_I2C0_ROUTEEN - I2C0 Pin Enable
912
GPIO_I2C0_SCLROUTE - SCL Port/Pin Select
912
GPIO_I2C0_SDAROUTE - SDA Port/Pin Select
913
GPIO_I2C1_ROUTEEN - I2C1 Pin Enable
913
GPIO_I2C1_SCLROUTE - SCL Port/Pin Select
914
GPIO_I2C1_SDAROUTE - SDA Port/Pin Select
914
GPIO_KEYSCAN_ROUTEEN - KEYSCAN Pin Enable
915
GPIO_KEYSCAN_COLOUT0ROUTE - COLOUT0 Port/Pin Select
916
GPIO_KEYSCAN_COLOUT1ROUTE - COLOUT1 Port/Pin Select
916
GPIO_KEYSCAN_COLOUT2ROUTE - COLOUT2 Port/Pin Select
917
GPIO_KEYSCAN_COLOUT3ROUTE - COLOUT3 Port/Pin Select
917
GPIO_KEYSCAN_COLOUT4ROUTE - COLOUT4 Port/Pin Select
918
GPIO_KEYSCAN_COLOUT5ROUTE - COLOUT5 Port/Pin Select
918
GPIO_KEYSCAN_COLOUT6ROUTE - COLOUT6 Port/Pin Select
919
GPIO_KEYSCAN_COLOUT7ROUTE - COLOUT7 Port/Pin Select
919
GPIO_KEYSCAN_ROWSENSE0ROUTE - ROWSENSE0 Port/Pin Select
920
GPIO_KEYSCAN_ROWSENSE1ROUTE - ROWSENSE1 Port/Pin Select
920
GPIO_KEYSCAN_ROWSENSE2ROUTE - ROWSENSE2 Port/Pin Select
921
GPIO_KEYSCAN_ROWSENSE3ROUTE - ROWSENSE3 Port/Pin Select
921
GPIO_KEYSCAN_ROWSENSE4ROUTE - ROWSENSE4 Port/Pin Select
922
GPIO_KEYSCAN_ROWSENSE5ROUTE - ROWSENSE5 Port/Pin Select
922
GPIO_LESENSE_ROUTEEN - LESENSE Pin Enable
923
GPIO_LESENSE_CH0OUTROUTE - CH0OUT Port/Pin Select
924
GPIO_LESENSE_CH1OUTROUTE - CH1OUT Port/Pin Select
925
GPIO_LESENSE_CH2OUTROUTE - CH2OUT Port/Pin Select
925
GPIO_LESENSE_CH3OUTROUTE - CH3OUT Port/Pin Select
926
GPIO_LESENSE_CH4OUTROUTE - CH4OUT Port/Pin Select
926
GPIO_LESENSE_CH5OUTROUTE - CH5OUT Port/Pin Select
927
GPIO_LESENSE_CH6OUTROUTE - CH6OUT Port/Pin Select
927
GPIO_LESENSE_CH7OUTROUTE - CH7OUT Port/Pin Select
928
GPIO_LESENSE_CH8OUTROUTE - CH8OUT Port/Pin Select
928
GPIO_LESENSE_CH9OUTROUTE - CH9OUT Port/Pin Select
929
GPIO_LESENSE_CH10OUTROUTE - CH10OUT Port/Pin Select
929
GPIO_LESENSE_CH11OUTROUTE - CH11OUT Port/Pin Select
930
GPIO_LESENSE_CH12OUTROUTE - CH12OUT Port/Pin Select
930
GPIO_LESENSE_CH13OUTROUTE - CH13OUT Port/Pin Select
931
GPIO_LESENSE_CH14OUTROUTE - CH14OUT Port/Pin Select
931
GPIO_LESENSE_CH15OUTROUTE - CH15OUT Port/Pin Select
932
GPIO_LETIMER_ROUTEEN - LETIMER Pin Enable
932
GPIO_LETIMER_OUT0ROUTE - OUT0 Port/Pin Select
933
GPIO_LETIMER_OUT1ROUTE - OUT1 Port/Pin Select
933
GPIO_MODEM_ROUTEEN - MODEM Pin Enable
934
GPIO_MODEM_ANT0ROUTE - ANT0 Port/Pin Select
935
GPIO_MODEM_ANT1ROUTE - ANT1 Port/Pin Select
936
GPIO_MODEM_ANTROLLOVERROUTE - ANTROLLOVER Port/Pin Select
936
GPIO_MODEM_ANTRR0ROUTE - ANTRR0 Port/Pin Select
937
GPIO_MODEM_ANTRR1ROUTE - ANTRR1 Port/Pin Select
937
GPIO_MODEM_ANTRR2ROUTE - ANTRR2 Port/Pin Select
938
GPIO_MODEM_ANTRR3ROUTE - ANTRR3 Port/Pin Select
938
GPIO_MODEM_ANTRR4ROUTE - ANTRR4 Port/Pin Select
939
GPIO_MODEM_ANTRR5ROUTE - ANTRR5 Port/Pin Select
939
GPIO_MODEM_ANTSWENROUTE - ANTSWEN Port/Pin Select
940
GPIO_MODEM_ANTSWUSROUTE - ANTSWUS Port/Pin Select
940
GPIO_MODEM_ANTTRIGROUTE - ANTTRIG Port/Pin Select
941
GPIO_MODEM_ANTTRIGSTOPROUTE - ANTTRIGSTOP Port/Pin Select
941
GPIO_MODEM_DCLKROUTE - DCLK Port/Pin Select
942
GPIO_MODEM_DINROUTE - DIN Port/Pin Select
942
GPIO_MODEM_DOUTROUTE - DOUT Port/Pin Select
943
GPIO_PCNT0_S0INROUTE - S0IN Port/Pin Select
943
GPIO_PCNT0_S1INROUTE - S1IN Port/Pin Select
944
GPIO_PRS0_ROUTEEN - PRS0 Pin Enable
945
GPIO_PRS0_ASYNCH0ROUTE - ASYNCH0 Port/Pin Select
946
GPIO_PRS0_ASYNCH2ROUTE - ASYNCH2 Port/Pin Select
947
GPIO_PRS0_ASYNCH3ROUTE - ASYNCH3 Port/Pin Select
948
GPIO_PRS0_ASYNCH4ROUTE - ASYNCH4 Port/Pin Select
948
GPIO_PRS0_ASYNCH5ROUTE - ASYNCH5 Port/Pin Select
949
GPIO_PRS0_ASYNCH6ROUTE - ASYNCH6 Port/Pin Select
949
GPIO_PRS0_ASYNCH7ROUTE - ASYNCH7 Port/Pin Select
950
GPIO_PRS0_ASYNCH8ROUTE - ASYNCH8 Port/Pin Select
950
GPIO_PRS0_ASYNCH9ROUTE - ASYNCH9 Port/Pin Select
951
GPIO_PRS0_ASYNCH10ROUTE - ASYNCH10 Port/Pin Select
951
GPIO_PRS0_ASYNCH11ROUTE - ASYNCH11 Port/Pin Select
952
GPIO_PRS0_SYNCH0ROUTE - SYNCH0 Port/Pin Select
952
GPIO_PRS0_SYNCH1ROUTE - SYNCH1 Port/Pin Select
953
GPIO_PRS0_SYNCH2ROUTE - SYNCH2 Port/Pin Select
953
GPIO_PRS0_SYNCH3ROUTE - SYNCH3 Port/Pin Select
954
GPIO_SYXO0_BUFOUTREQINASYNCROUTE - BUFOUTREQINASYNC Port/Pin Select
954
GPIO_TIMER0_ROUTEEN - TIMER0 Pin Enable
955
GPIO_TIMER0_CC0ROUTE - CC0 Port/Pin Select
956
GPIO_TIMER0_CC1ROUTE - CC1 Port/Pin Select
956
GPIO_TIMER0_CC2ROUTE - CC2 Port/Pin Select
957
GPIO_TIMER0_CDTI1ROUTE - CDTI1 Port/Pin Select
958
GPIO_TIMER0_CDTI2ROUTE - CDTI2 Port/Pin Select
958
GPIO_TIMER1_ROUTEEN - TIMER1 Pin Enable
959
GPIO_TIMER1_CC0ROUTE - CC0 Port/Pin Select
960
GPIO_TIMER1_CC1ROUTE - CC1 Port/Pin Select
960
GPIO_TIMER1_CC2ROUTE - CC2 Port/Pin Select
961
GPIO_TIMER1_CDTI0ROUTE - CDTI0 Port/Pin Select
961
GPIO_TIMER1_CDTI1ROUTE - CDTI1 Port/Pin Select
962
GPIO_TIMER1_CDTI2ROUTE - CDTI2 Port/Pin Select
962
GPIO_TIMER2_ROUTEEN - TIMER2 Pin Enable
963
GPIO_TIMER2_CC0ROUTE - CC0 Port/Pin Select
964
GPIO_TIMER2_CC1ROUTE - CC1 Port/Pin Select
964
GPIO_TIMER2_CC2ROUTE - CC2 Port/Pin Select
965
GPIO_TIMER2_CDTI0ROUTE - CDTI0 Port/Pin Select
965
GPIO_TIMER2_CDTI1ROUTE - CDTI1 Port/Pin Select
966
GPIO_TIMER2_CDTI2ROUTE - CDTI2 Port/Pin Select
966
GPIO_TIMER3_ROUTEEN - TIMER3 Pin Enable
967
GPIO_TIMER3_CC0ROUTE - CC0 Port/Pin Select
968
GPIO_TIMER3_CC1ROUTE - CC1 Port/Pin Select
968
GPIO_TIMER3_CC2ROUTE - CC2 Port/Pin Select
969
GPIO_TIMER3_CDTI0ROUTE - CDTI0 Port/Pin Select
969
GPIO_TIMER3_CDTI1ROUTE - CDTI1 Port/Pin Select
970
GPIO_TIMER3_CDTI2ROUTE - CDTI2 Port/Pin Select
970
GPIO_TIMER4_ROUTEEN - TIMER4 Pin Enable
971
GPIO_TIMER4_CC0ROUTE - CC0 Port/Pin Select
972
GPIO_TIMER4_CC1ROUTE - CC1 Port/Pin Select
972
GPIO_TIMER4_CC2ROUTE - CC2 Port/Pin Select
973
GPIO_TIMER4_CDTI0ROUTE - CDTI0 Port/Pin Select
973
GPIO_TIMER4_CDTI1ROUTE - CDTI1 Port/Pin Select
974
GPIO_TIMER4_CDTI2ROUTE - CDTI2 Port/Pin Select
974
GPIO_USART0_ROUTEEN - USART0 Pin Enable
975
GPIO_USART0_CSROUTE - CS Port/Pin Select
976
GPIO_USART0_CTSROUTE - CTS Port/Pin Select
976
GPIO_USART0_RTSROUTE - RTS Port/Pin Select
977
GPIO_USART0_RXROUTE - RX Port/Pin Select
977
GPIO_USART0_CLKROUTE - SCLK Port/Pin Select
978
GPIO_USART0_TXROUTE - TX Port/Pin Select
978
LDMA - Linked DMA
979
Introduction
979
Features
980
Block Diagram
981
Functional Description
982
Channel Descriptor
982
Channel Configuration
987
Channel Select Configuration
987
Starting a Transfer
987
Managing Transfer Errors
988
Arbitration
988
Channel Descriptor Data Structure
990
Interaction with the EMU
993
Interrupts
994
Debugging
994
Examples
994
Single Direct Register DMA Transfer
994
Descriptor Linked List
995
Descriptor List with Looping
998
Simple Inter-Channel Synchronization
999
Copy
1001
Ping-Pong
1003
Scatter-Gather
1004
LDMA Source Selection Details
1004
LDMA Source Selection Details
1005
LDMA Register Map
1007
LDMA Register Description
1010
LDMA_IPVERSION - DMA Channel Request Clear Register
1010
LDMA_EN - DMA Module Enable Disable Register
1010
LDMA_CTRL - DMA Control Register
1011
LDMA_STATUS - DMA Status Register
1012
LDMA_SYNCSWSET - DMA Sync Trig Sw Set Register
1013
LDMA_SYNCSWCLR - DMA Sync Trig Sw Clear Register
1013
LDMA_SYNCHWEN - DMA Sync HW Trigger Enable Register
1014
LDMA_SYNCHWSEL - DMA Sync HW Trigger Selection Register
1015
LDMA_SYNCSTATUS - DMA Sync Trigger Status Register
1016
LDMA_CHEN - DMA Channel Enable Register
1016
LDMA_CHDIS - DMA Channel Disable Register
1017
LDMA_CHSTATUS - DMA Channel Status Register
1017
LDMA_CHBUSY - DMA Channel Busy Register
1018
LDMA_CHDONE - DMA Channel Linking Done Register
1019
LDMA_DBGHALT - DMA Channel Debug Halt Register
1020
LDMA_SWREQ - DMA Channel Software Transfer Request
1020
LDMA_REQDIS - DMA Channel Request Disable Register
1021
LDMA_REQPEND - DMA Channel Requests Pending Register
1021
LDMA_LINKLOAD - DMA Channel Link Load Register
1022
LDMA_REQCLEAR - DMA Channel Request Clear Register
1022
LDMA_IF - Interrupt Flag Register
1023
LDMA_IEN - Interrupt Enable Register
1024
Ldma_Chx_Cfg - Channel Configuration Register
1025
Ldma_Chx_Loop - Channel Loop Counter Register
1026
Ldma_Chx_Ctrl - Channel Descriptor Control Word Register
1027
Ldma_Chx_Src - Channel Descriptor Source Address
1030
Ldma_Chx_Dst - Channel Descriptor Destination Address
1030
Ldma_Chx_Link - Channel Descriptor Link Address
1031
LDMAXBAR Register Map
1031
LDMAXBAR Register Description
1032
LDMAXBAR_IPVERSION - IP Veersion ID
1032
Ldmaxbar_Chx_Reqsel - Channel Peripheral Request Select Reg
1032
WDOG - Watch Dog Timer
1033
Introduction
1033
Features
1033
Functional Description
1034
Clock Source
1034
Debug Functionality
1034
Energy Mode Handling
1034
Warning Interrupt
1034
Window Interrupt
1035
PRS as Watchdog Clear
1036
PRS Rising Edge Monitoring
1036
WDOG Register Map
1037
WDOG Register Description
1038
WDOG_IPVERSION - IP Version Register
1038
WDOG_EN - Enable Register
1038
WDOG_CFG - Configuration Register
1039
WDOG_CMD - Command Register
1042
WDOG_STATUS - Status Register
1042
WDOG_IF - Interrupt Flag Register
1043
WDOG_IEN - Interrupt Enable Register
1044
WDOG_LOCK - Lock Register
1045
WDOG_SYNCBUSY - Synchronization Busy Register
1045
LCD - Liquid Crystal Display Driver
1046
Introduction
1046
Features
1046
Functional Description
1047
LCD Frame Rates
1048
LCD Multiplexing, Bias, and Wave Settings
1049
LCD Waveform Examples
1050
Type a Waveforms with Charge Redistribution
1067
LCD Contrast
1075
Voltage Levels and Mode Selection
1075
Data Update
1076
Direct Segment Control (DSC)
1077
Frame Counter (FC)
1078
Display Counter
1079
LCD Interrupt
1079
LCD DMA Transfer
1079
Blink, Blank, and Animation Features
1079
LCD in Low Energy Modes
1083
LCD Synchronization
1083
LCD Register Map
1084
LCD Register Description
1086
Lcd_Ipversion - Ipversion
1086
LCD_EN - Enable
1087
LCD_SWRST - Software Reset
1087
LCD_CTRL - Control Register
1088
LCD_CMD - Command Register
1089
LCD_DISPCTRL - Display Control Register
1090
LCD_BACFG - Blink and Animation Config Register
1091
LCD_BACTRL - Blink and Animation Control Register
1092
LCD_STATUS - Status Register
1094
LCD_AREGA - Animation Register a
1094
LCD_AREGB - Animation Register B
1095
LCD_IF - Interrupt Enable Register
1095
LCD_IEN - Interrupt Enable
1096
LCD_BIASCTRL - Analog BIAS Control
1097
LCD_DISPCTRLX - Display Control Extended
1098
LCD_SEGD0 - Segment Data Register 0
1099
LCD_SEGD1 - Segment Data Register 1
1099
LCD_SEGD2 - Segment Data Register 2
1100
LCD_SEGD3 - Segment Data Register 3
1100
LCD_UPDATECTRL - Update Control
1101
LCD_FRAMERATE - Frame Rate
1102
PCNT - Pulse Counter
1103
Introduction
1103
Features
1103
Pulse Counter Modes
1104
Hysteresis
1111
Auxiliary Counter
1112
Register Access
1112
Clock Sources
1112
Input Filter
1113
Edge Polarity
1113
PRS and Pcntn_S0In,Pcntn_S1In Inputs
1113
Interrupts
1113
PCNT Register Map
1115
PCNT Register Description
1117
PCNT_IPVERSION - IP Version ID
1117
PCNT_EN - Module Enable Register
1117
PCNT_SWRST - Software Reset Register
1118
PCNT_CFG - Configuration Register
1119
PCNT_CTRL - Control Register
1121
PCNT_CMD - Command Register
1123
PCNT_STATUS - Status Register
1124
PCNT_IF - Interrupt Flag Register
1125
PCNT_IEN - Interrupt Enable Register
1126
PCNT_CNT - Counter Value Register
1126
PCNT_AUXCNT - Auxiliary Counter Value Register
1127
PCNT_TOP - Top Value Register
1127
PCNT_TOPB - Counter Top Value Buffer Register
1128
PCNT_OVSCTRL - Oversampling Control Register
1128
PCNT_SYNCBUSY - Synchronization Busy Register
1129
PCNT_LOCK - Configuration Lock Register
1130
LESENSE - Low Energy Sensor Interface
1131
Introduction
1131
Features
1131
Interface Descriptions
1132
Functional Description
1133
Channel Configuration
1134
Scan Sequence
1135
Sensor Timing
1136
Sensor Interaction
1138
Sensor Sampling
1139
Sensor Evaluation
1140
Threshold Comparison
1140
Sliding Window
1141
Step Detection
1141
Decoder
1142
Measurement Results
1144
DMA Requests
1144
Prs
1145
Programmer's Model
1145
LESENSE Register Map
1146
LESENSE Register Description
1149
Lesense_Ipversion - Ipversion
1149
LESENSE_EN - Enable
1150
LESENSE_SWRST - Software Reset Register
1150
LESENSE_CFG - Configuration
1151
LESENSE_TIMCTRL - Timing Control
1153
LESENSE_PERCTRL - Peripheral Control
1155
LESENSE_DECCTRL - Decoder Control
1157
LESENSE_EVALCTRL - LESENSE Evaluation
1158
LESENSE_PRSCTRL - PRS Control
1158
LESENSE_CMD - Command
1159
LESENSE_CHEN - Channel Enable
1159
LESENSE_SCANRES - Scan Result
1160
LESENSE_STATUS - Status
1161
LESENSE_RESCOUNT - Result FIFO Count
1162
LESENSE_CURCH - Current Channel Index
1163
LESENSE_DECSTATE - Current Decoder State
1163
LESENSE_SENSORSTATE - Sensor State
1164
LESENSE_IDLECONF - IDLE Configuration
1165
LESENSE_SYNCBUSY - Synchronization
1169
LESENSE_IF - Interrupt Flags
1170
LESENSE_IEN - Interrupt Enables
1172
Lesense_Chx_Timing - Scan Configuration
1173
Lesense_Chx_Interact - Scan Configuration
1174
Lesense_Chx_Evalthres - Scan Confguration
1177
Lesense_Stx_Arc - State Transition Arc
1178
VDAC - Digital to Analog Converter
1180
Introduction
1180
Features
1181
Functional Description
1182
Power Supply
1182
I/O Pin Considerations
1182
Enabling and Disabling a Channel
1183
Clock Selection
1184
Conversions
1185
Conversion Trigger
1186
Refresh Trigger
1186
PRS Communication
1186
Reference Selection
1187
Power Modes
1187
Warmup Time and Initial Conversion
1187
Output Mode
1188
Internal Timers
1188
Fifo
1189
Keepwarm Sub-Modes
1189
LDMA Interface
1189
LESENSE Operation
1191
VDAC Output Configuration
1191
VDAC Register Map
1193
VDAC Register Description
1194
Vdac_Ipversion - Ipversion
1194
VDAC_EN - Module Enable
1195
VDAC_SWRST - Software Reset Register
1195
VDAC_STATUS - Status Register
1199
VDAC_CH0CFG - Channel 0 Config Register
1201
VDAC_CH1CFG - Channel 1 Config Register
1203
VDAC_CMD - Command Register
1205
VDAC_IF - Interrupt Flag Register
1206
VDAC_IEN - Interrupt Enable Register
1208
VDAC_CH0F - Channel 0 Data Write Fifo
1209
VDAC_CH1F - Channel 1 Data Write Fifo
1209
ACMP - Analog Comparator
1212
Introduction
1212
Features
1212
Functional Description
1213
Configuration and Control
1214
Warmup Time
1214
Response Time
1214
Hysteresis
1215
LESENSE Interface
1215
Supply Voltage Monitoring (VSENSE)
1215
VREFDIV Sources
1216
Interrupts and PRS Output
1218
ACMP Register Map
1219
ACMP Register Description
1220
ACMP_SWRST - Software Reset
1221
ACMP_CFG - Configuration Register
1222
ACMP_CTRL - Control Register
1223
ACMP_STATUS - Status Register
1229
ACMP_IF - Interrupt Flag Register
1230
ACMP_SYNCBUSY - Syncbusy
1231
KEYSCAN - Keyboard Scan
1232
Introduction
1232
Features
1232
Functional Description
1233
Row and Column Configuration
1233
Clocking and Timing
1233
Scanning
1234
Wake on Key
1235
KEYSCAN Register Map
1236
KEYSCAN Register Description
1237
KEYSCAN_EN - Enable
1237
KEYSCAN_SWRST - Software Reset
1238
KEYSCAN_CFG - Config
1239
KEYSCAN_DELAY - Delay
1241
KEYSCAN_STATUS - Status
1243
KEYSCAN_IF - Interrupt Flags
1244
KEYSCAN_IEN - Interrupt Enables
1245
Revision History
1246
Appendix 1. Abbreviations
1248
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