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Summary of Contents for PLX Technology PEX 8615
- Page 1 PEX 8615 Quick Start Hardware Design Guide Version 1.2 December 2009 Website: www.plxtech.com Technical Support: www.plxtech.com/support Copyright © 2009 by PLX Technology, Inc. All Rights Reserved – Version 1.2 December 18, 2009...
- Page 2 © 2009 PLX Technology, Inc. All Rights Reserved. PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX products.
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Page 3: Table Of Contents
1.4.1 Spread Spectrum Clock Isolation .................... 6 1.5 Channel ............................7 2 PCB Layout and Stackup Considerations ................... 8 2.1 PEX 8615 BGA Routing Escape and De-Coupling Capacitor Placement ........8 2.2 Add-in Board Routing ........................9 2.3 System Board Routing ........................9 ... - Page 4 Figure 10. Enable NT Function with NT Strapping Balls ................. 11 Figure 11. Disable NT Function ......................11 Figure 12. SHPC Interface to PEX 8615 Block Diagram ................ 12 Figure 13. JTAG Interface Block Diagram ....................13 Figure 14. I C Interface Block Diagram ....................
- Page 5 PEX 8615, or for any damage or loss caused by deletion of data as a result of malfunction or repair.
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Page 6: 1 Pci Express Link Interface
PLX’s PEX 8615 is a 12-Lane, 12-Port PCI Express 2.0 (Gen 2) compliant switch. PCI Express 2.0 supports transfer rates of 2.5 GT/s and 5.0 GT/s per Lane. The PEX 8615 supports the required 2.5 GT/s as well as the optional 5.0 GT/s on its physical interface. -
Page 7: Transmitter
Longer Links should use 6.0 dB, whereas shorter Links can use the 3.5 dB level. The standard de-emphasis level is selectable by way of the PEX 8615 Link Control 2 register Selectable De- Emphasis bit (Configuration register, offset 98h[bit 6]). - Page 8 In addition to supporting the standard de-emphasis levels, the PEX 8615 has a number of programmable registers to control the Transmitter’s characteristics, such as drive level and de-emphasis. Registers at offsets B98h to BA4h are the SerDes Drive Level registers. Registers at offsets BA8h to BB4h are the Post-Cursor Emphasis Level registers.
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Page 9: Receiver
The PEX 8615 provides a programmable receive equalization function. Each port has a set of Receiver Equalizer registers, located at offsets BB8h and BBCh, to control a group of 12 SerDes. Each individual SerDes has a 4-bit control word. -
Page 10: Figure 3. Transport Delay Delta
Reference Clock transport delay delta. The PEX 8615 PEX_REFCLKn/p signal is the Reference Clock Input buffer. It has an internal DC-biasing circuit, and hence, should be AC-coupled from the RefClk source driver. Use 0.01 to 0.1 µF capacitors (0603 or 0402-... -
Page 11: Spread Spectrum Clocking (Ssc)
(CFC), the downstream interface will not link-up. To solve this problem, a system designer using the PEX 8615 can either use the SSC isolation feature (explained in section 1.4.1) or provide a means to pass the SSC clock to the downstream component. -
Page 12: Channel
Figure 6 demonstrates a mixed SSC and CFC system that might exist when utilizing PEX 8615’s SSC isolation feature. NOTE: When SSC isolation is used, the SSC clock must be connected to PEX_REFCLKp/n. Downstream Downstream REFCLKp /n Device Device REFCLKp /n . -
Page 13: 2 Pcb Layout And Stackup Considerations
“dog-bone” nets from the pad to a via which will connect it with an internal power or ground plane. The PEX 8615 places all Transmitter differential pairs on the outer two rows of balls and Receiver differential pairs on rows three and four. -
Page 14: Add-In Board Routing
Add-in Board Routing The PEX 8615 Transmitter pairs escape on the top layer, but at some point must route to the bottom layer, to connect to the gold fingers. If a logic analyzer midbus footprint is placed in the routing path, the layer transition can occur at that point. -
Page 15: Midbus Routing
PCBs with six or more layers. Microstrip and stripline traces each have their own properties, which must be weighed when determining which type of trace to use. PEX 8615 Quick Start Hardware Design Guide – Version 1.2 Copyright © 2009 by PLX Technology, Inc. All rights reserved. -
Page 16: 3 Nt Function
STRAP_NT_UPSTREAM_PORTSEL[3:0] to select the NT Port. Make sure the NT port selected is NOT the same as the upstream port. Method 2. Enable the NT function and configure the NT Port through the serial EEPROM, when the PEX 8615 switch is powering up. -
Page 17: 4 Hot Plug Circuitry
C Bus. To use 40-I/O expander(s), a register bit within the PEX 8615 must be Set, and boot with serial EEPROM is essential. After the PEX 8615 is powered up, the state machine inside the PEX 8615 scans the number of I/O expander ICs connecting to the I C Bus, starting from Address 000h, in ascending order. -
Page 18: 5 Jtag Interface
At the board level, pull JTAG_TDI, JTAG_TMS, and JTAG_TCK up to 2.5V with 1-kohm to 5-kohm resistors. Pull JTAG_TRST# down to VSS with a 1-kohm to 5-kohm resistor. Because the PEX 8615 JTAG clock frequency can be as high as 25 MHz, a 15-ohm series terminator can be added to TCK, TDI, and TDO, to improve signal quality. -
Page 19: C Interface
The PEX 8615 provides 12 Active-Low “Lane Good” Output balls for each PCI Express Lane on the device. These Output balls can be used to indicate the status of each PEX 8615 Lane. If a given Lane Good indicator is continually asserted, that lane is up and operating at 5 Gbps. -
Page 20: 8 Debug Functions
The SDM function is for viewing the 20-bit Receive Bus (elastic buffer exit) and 20-bit Transmit Bus of each Lane of the SerDes, in the PEX 8615. Two Strapping balls are used to enable either Debug mode function. Pulling down the STRAP_PROBE_MODE# ball enables the EPM function. Pulling down the STRAP_SERDES_MODE_EN# ball enables the SDM function. - Page 21 PEX_LANE_GOOD0# prb_outB0 xmit_dat0 N/C on ball T6 sclk/2 rclk/2 STRAP_NT_P2P_EN# trig_out trig_out STRAP_SPARE5# rcvr_dat19 GPIO27 xmit_dat19 GPIO26 xmit_dat18 PEX 8615 Quick Start Hardware Design Guide – Version 1.2 Copyright © 2009 by PLX Technology, Inc. All rights reserved.
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Page 22: 9 Pex 8615 Strapping Balls
PEX 8615 Strapping Balls The PEX 8615 has a total of 31 Strapping balls. Thirteen of them service different configuration functions. For the PEX 8615, none of the Strapping balls, including the Strapping balls for configuration, have internal pull-up or pull- down resistors. -
Page 23: 10 Power Supplies, Sequencing, And De-Coupling
Power Supplies, Sequencing, and De-Coupling The switch’s maximum power consumption is approximately 4.0W. Special cooling requirements may exist, depending upon the system environment. (Refer to the PEX 8615 Data Book for details). 10.1 Power Supplies The PEX 8615 has the following Power ball groups: VDD10 –... -
Page 24: Board-Level De-Coupling
0.0100 1.0V 0.0010 0.0001 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 Frequency - Hz Figure 15. Power Plane Impedance versus Frequency PEX 8615 Quick Start Hardware Design Guide – Version 1.2 Copyright © 2009 by PLX Technology, Inc. All rights reserved. -
Page 25: Figure 16. Capacitor Footprint Effects On Series Inductance
If holes do exist, capacitor values of some of the capacitors can be adjusted to fill them. PEX 8615 Quick Start Hardware Design Guide – Version 1.2 Copyright © 2009 by PLX Technology, Inc. All rights reserved. -
Page 26: 11 References
PCI Express Card Electromechanical (CEM) Specification, Revisions 1.0a and 1.1 Right the First Time: A Practical Handbook on High Speed PCB and System Design , by Lee Ritchie PEX 8615 Quick Start Hardware Design Guide – Version 1.2 Copyright © 2009 by PLX Technology, Inc. All rights reserved.
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