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Related Manuals for PLX Technology PEX 8604
Summary of Contents for PLX Technology PEX 8604
- Page 1 PEX 8604 Quick Start Hardware Design Guide Version 1.3 September 2010 Website: www.plxtech.com Technical Support: www.plxtech.com/support Copyright © 2009 by PLX Technology, Inc. All Rights Reserved – Version 1.3 September 22, 2010...
- Page 2 © 2009 PLX Technology, Inc. All Rights Reserved. PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX products.
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Page 3: Table Of Contents
Channel ............................7 PCB Layout and Stackup Considerations ....................8 PEX 8604 BGA Routing Escape and De-Coupling Capacitor Placement........8 Add-in Board Routing ........................9 System Board Routing ........................9 ... - Page 4 Figure 10. Enable NT Function with NT Strapping Balls ..................11 Figure 11. Disable NT Function ..........................11 Figure 12. SHPC Interface to PEX 8604 Block Diagram ..................12 Figure 13. JTAG Interface Block Diagram ....................... 13 ...
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Page 5: Preface
PEX 8604, or for any damage or loss caused by deletion of data as a result of malfunction or repair. -
Page 6: Pci Express Link Interface
PLX’s PEX 8604 is a 4-Lane, 4-Port PCI Express 2.0 (Gen 2) compliant switch. PCI Express 2.0 supports transfer rates of 2.5 GT/s and 5.0 GT/s per lane. The PEX 8604 supports the required 2.5 GT/s as well as the optional 5.0 GT/s on its physical interface. -
Page 7: Transmitter
Longer Links should use 6.0 dB, whereas shorter Links can use the 3.5 dB level. The standard de-emphasis level is selectable by way of the PEX 8604 Link Control 2 register Selectable De- Emphasis bit (Configuration register, offset 98h[bit 6]). -
Page 8: Receiver
The PEX 8604 provides a programmable receive equalization function. Each port has a set of Receiver Equalizer registers, located at offsets BB8h and BBCh, to control a group of 8 SerDes. Each individual SerDes has a 4-bit control word. -
Page 9: Reference Clock
Reference Clock transport delay delta. The PEX 8604 PEX_REFCLKn/p signal is the Reference Clock Input buffer. It has an internal DC-biasing circuit, and hence, should be AC-coupled from the RefClk source driver. Use 0.01 to 0.1 µF capacitors (0603 or 0402-... -
Page 10: Spread Spectrum Clocking (Ssc)
(CFC), the downstream interface will not link-up. To solve this problem, a system designer using the PEX 8604 can either use the SSC isolation feature (explained in section 1.4.1) or provide a means to pass the SSC clock to the downstream component. -
Page 11: Spread Spectrum Clock Isolation
SSC clocking. The PEX 8604 has the necessary buffering and logic required to allow the upstream port to operate using both an SSC clock and a constant frequency clock (CFC) source. This feature is enabled when the signal STRAP_SSC_ISO_ENABLE# is pulled down to VSS. -
Page 12: Channel
PLX provided HSPICE models. The PCI Express Base Specification, Revision 2.0 provides additional details for simulating a channel. PEX 8604 Quick Start Hardware Design Guide – Version 1.3 Copyright © 2009 by PLX Technology, Inc. All rights reserved... -
Page 13: Pcb Layout And Stackup Considerations
“dog-bone” nets from the pad to a via which will connect it with an internal power or ground plane. The PEX 8604 places all Transmitter and Receiver differential pairs on the outer two rows of balls. -
Page 14: Add-In Board Routing
Add-in Board Routing The PEX 8604 Transmitter pairs escape on the top layer, but at some point must route to the bottom layer, to connect to the gold fingers. If a logic analyzer midbus footprint is placed in the routing path, the layer transition can occur at that point. -
Page 15: Midbus Routing
PCBs with six or more layers. Microstrip and stripline traces each have their own properties, which must be weighed when determining which type of trace to use. PEX 8604 Quick Start Hardware Design Guide – Version 1.3 Copyright © 2009 by PLX Technology, Inc. All rights reserved... -
Page 16: Non-Transparent Port Function
STRAP_NT_UPSTREAM_PORTSEL[3:0] to select the NT Port. Make sure the NT port selected is NOT the same as the upstream port. Method 2. Enable the NT function and configure the NT Port through the serial EEPROM, when the PEX 8604 switch is powering up. -
Page 17: Hot-Plug Circuitry
C Bus. To use 40-I/O expander(s), a register bit within the PEX 8604 must be Set, and boot with serial EEPROM is essential. After the PEX 8604 is powered up, the state machine inside the PEX 8604 scans the number of I/O expander ICs connecting to the I C Bus, starting from Address 000h, in ascending order. -
Page 18: Jtag Interface
At the board level, pull JTAG_TDI, JTAG_TMS, and JTAG_TCK up to 2.5V with 1-kohm to 5-kohm resistors. Pull JTAG_TRST# down to VSS with a 1-kohm to 5-kohm resistor. Because the PEX 8604 JTAG clock frequency can be as high as 25 MHz, a 15-ohm series terminator can be added to TCK, TDI, and TDO, to improve signal quality. -
Page 19: C Interface
The PEX 8604 provides 4 Active-Low “Lane Good” Output balls for each PCI Express lane on the device. These Output balls can be used to indicate the status of each PEX 8604 Lane. If a given Lane Good indicator is continually asserted, that lane is up and operating at 5 Gbps. -
Page 20: Debug Functions
The SDM function is for viewing the 20-bit Receive Bus (elastic buffer exit) and 20-bit Transmit Bus of each Lane of the SerDes, in the PEX 8604. Two Strapping balls are used to enable either Debug mode function. Pulling down the STRAP_PROBE_MODE# ball enables the EPM function. Pulling down the STRAP_SERDES_MODE_EN# ball enables the SDM function. - Page 21 N/C on ball L14 prb_outB2 xmit_dat2 PEX_LANE_GOOD1# prb_outB1 xmit_dat01 PEX_LANE_GOOD0# prb_outB0 xmit_dat0 N/C on ball N1 sclk/2 rclk/2 STRAP_NT_P2P_EN# trig_out trig_out PEX 8604 Quick Start Hardware Design Guide – Version 1.3 Copyright © 2009 by PLX Technology, Inc. All rights reserved...
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Page 22: Pex 8604 Strapping Balls
PEX 8604 Strapping Balls The PEX 8604 has a total of 28 Strapping balls. Eleven of them service different configuration functions. For the PEX 8604, none of the Strapping balls, including the Strapping balls for configuration, have internal pull-up or pull- down resistors. -
Page 23: Power Supplies, Sequencing, And De-Coupling
Power Supplies, Sequencing, and De-Coupling The switch’s maximum power consumption is approximately 2.6W. Special cooling requirements may exist, depending upon the system environment. (Refer to the PEX 8604 Data Book for details). 10.1 Power Supplies The PEX 8604 has the following Power ball groups: VDD10 –... -
Page 24: Board-Level De-Coupling
0.0100 1.0V 0.0010 0.0001 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 Frequency - Hz Figure 15. Power Plane Impedance versus Frequency PEX 8604 Quick Start Hardware Design Guide – Version 1.3 Copyright © 2009 by PLX Technology, Inc. All rights reserved... -
Page 25: Figure 16. Capacitor Footprint Effects On Series Inductance
If holes do exist, capacitor values of some of the capacitors can be adjusted to fill them. PEX 8604 Quick Start Hardware Design Guide – Version 1.3 Copyright © 2009 by PLX Technology, Inc. All rights reserved... -
Page 26: References
PCI Express Card Electromechanical (CEM) Specification, Revisions 1.0a and 1.1 Right the First Time: A Practical Handbook on High Speed PCB and System Design , by Lee Ritchie PEX 8604 Quick Start Hardware Design Guide – Version 1.3 Copyright © 2009 by PLX Technology, Inc. All rights reserved...
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