Table of Contents
Related Manuals for PLX Technology PEX 8606
Summary of Contents for PLX Technology PEX 8606
- Page 1 PEX 8606 Quick Start Hardware Design Guide Version 1.2 December 2009 Website: www.plxtech.com Technical Support: www.plxtech.com/support Copyright © 2009 by PLX Technology, Inc. All Rights Reserved – Version 1.2 December 18, 2009...
- Page 2 © 2009 PLX Technology, Inc. All Rights Reserved. PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX products.
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Page 3: Table Of Contents
Channel ............................8 PCB Layout and Stackup Considerations ....................9 PEX 8606 BGA Routing Escape and De-Coupling Capacitor Placement........9 Add-in Board Routing ........................10 System Board Routing ........................10 ... - Page 4 Figure 10. Enable NT Function with NT Strapping Balls ..................12 Figure 11. Disable NT Function ..........................12 Figure 12. SHPC Interface to PEX 8606 Block Diagram ..................13 Figure 13. JTAG Interface Block Diagram ....................... 14 Figure 14. I C Interface Block Diagram ........................
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Page 5: Preface
PEX 8606, or for any damage or loss caused by deletion of data as a result of malfunction or repair. -
Page 6: Pci Express Link Interface
PLX’s PEX 8606 is a 6-Lane, 6-Port PCI Express 2.0 (Gen 2) compliant switch. PCI Express 2.0 supports transfer rates of 2.5 GT/s and 5.0 GT/s per Lane. The PEX 8606 supports the required 2.5 GT/s as well as the optional 5.0 GT/s on its physical interface. The Physical Media Attachment (PMA) Layer for each Lane is implemented as a SerDes transceiver, which is composed of a transmit path and receive path. -
Page 7: Transmitter
Set their de-emphasis level, accordingly. Longer Links should use 6.0 dB, whereas shorter Links can use the 3.5 dB level. The standard de-emphasis level is selectable by way of the PEX 8606 Link Control 2 register Selectable De-Emphasis bit (Configuration register, offset 98h[bit 6]). - Page 8 In addition to supporting the standard de-emphasis levels, the PEX 8606 has a number of programmable registers to control the Transmitter’s characteristics, such as drive level and de-emphasis. Registers at offsets B98h and BA0h are the SerDes Drive Level registers. Registers at offsets BA8h and BB0h are the Post-Cursor Emphasis Level registers.
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Page 9: Receiver
Receiver equalization only needs to be used on longer channels. The PEX 8606 provides a programmable receive equalization function. Each port has a set of Receiver Equalizer registers, located at offsets BB8h and BBCh, to control a group of 8 SerDes. Each individual has a 4-bit control word. -
Page 10: Figure 3. Transport Delay Delta
Reference Clock transport delay delta. The PEX 8606 PEX_REFCLKn/p signal is the Reference Clock Input buffer. It has an internal DC-biasing circuit, and hence, should be AC-coupled from the RefClk source driver. Use 0.01 to 0.1 µF capacitors (0603 or 0402-size) to AC-couple the Reference Clock input, as illustrated in Figure Transport Delay Delta = (T1+T2+T3) –... -
Page 11: Spread Spectrum Clocking (Ssc)
SSC clocking. The PEX 8606 has the necessary buffering and logic required to allow the upstream port to operate using both an SSC clock and a constant frequency clock (CFC) source. This feature is enabled when the signal STRAP_SSC_ISO_ENABLE# is pulled down to VSS. -
Page 12: Figure 5. Single Reference Clock Scheme (Strap_Ssc_Iso_Enable# Pulled High)
) RefClk PEX_REFCLKp /n Port 0 Generator Upstream Device Figure 5. Single reference clock scheme (STRAP_SSC_ISO_ENABLE# pulled high) PEX 8606 Quick Start Hardware Design Guide – Version 1.2 Copyright © 2009 by PLX Technology, Inc. All rights reserved... -
Page 13: Channel
PLX provided HSPICE models. The PCI Express Base Specification, Revision 2.0 provides additional details for simulating a channel. PEX 8606 Quick Start Hardware Design Guide – Version 1.2 Copyright © 2009 by PLX Technology, Inc. All rights reserved... -
Page 14: Pcb Layout And Stackup Considerations
“dog-bone” nets from the pad to a via which will connect it with an internal power or ground plane. The PEX 8606 places all Transmitter and Receiver differential pairs on the outer two rows of balls. This means it should take one signal layer in a PCB stackup to escape the differential pairs from the BGA. -
Page 15: Add-In Board Routing
Add-in Board Routing The PEX 8606 Transmitter pairs escape on the top layer, but at some point must route to the bottom layer, to connect to the gold fingers. If a logic analyzer midbus footprint is placed in the routing path, the layer transition can occur at that point. -
Page 16: Midbus Routing
PEX 8606 Quick Start Hardware Design Guide – Version 1.2 Copyright © 2009 by PLX Technology, Inc. All rights reserved... -
Page 17: Non-Transparent Port Function
3 Non-Transparent Port Function The PEX 8606 supports Non-Transparent mode (NT mode) function. Any of the possible 16 Ports can be configured as the NT Port. There are three ways to enable the NT function and configure the NT Port for the PEX 8606. -
Page 18: Hot-Plug Circuitry
PEX 8606 must be set, and boot with serial EEPROM is essential. After the PEX 8606 is powered up, the state machine inside the PEX 8606 scans the number of I/O expander ICs connecting to the I C Bus, starting from Address 000h, in ascending order. -
Page 19: Jtag Interface
JTAG Interface The PEX 8606 supports a five-ball JTAG Boundary Scan interface. The JTAG interface consists of the following signals: JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO JTAG_TRST# At the board level, pull JTAG_TDI, JTAG_TMS, and JTAG_TCK up to 2.5V with 1-kohm to 5-kohm resistors. -
Page 20: C Interface
The PEX 8606 provides 6 Active-Low “Lane Good” Output balls for each PCI Express Lane on the device. These Output balls can be used to indicate the status of each PEX 8606 Lane. If a given Lane Good indicator is continually asserted, that lane is up and operating at 5 Gbps. If a given Lane Good indicator is blinking, that lane is up and operating at 2.5 Gbps. -
Page 21: Debug Functions
The optional Debug function is primarily intended for prototyping activities. Its use requires assistance from PLX Technical Support.) Two major debug functions of the PEX 8606 are External Probe mode (EPM) and SerDes Debug mode (SDM). The EPM function is for viewing the internal state machines and control signals of the station-based modules and the core-based module. - Page 22 N/C on ball L14 prb_outB2 xmit_dat2 PEX_LANE_GOOD1# prb_outB1 xmit_dat01 PEX_LANE_GOOD0# prb_outB0 xmit_dat0 N/C on ball N1 sclk/2 rclk/2 STRAP_NT_P2P_EN# trig_out trig_out PEX 8606 Quick Start Hardware Design Guide – Version 1.2 Copyright © 2009 by PLX Technology, Inc. All rights reserved...
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Page 23: Pex 8606 Strapping Balls
PEX 8606 Strapping Balls The PEX 8606 has a total of 28 Strapping balls. Eleven of them service different configuration functions. For the PEX 8606, none of the Strapping balls, including the Strapping balls for configuration, have internal pull-up or pull-down resistors. If the Port configuration is fixed, use external pull-up or pull-down resistors and hardwire these Strapping balls to the values corresponding to the Port configuration desired. -
Page 24: Power Supplies, Sequencing, And De-Coupling
Power Supplies, Sequencing, and De-Coupling The switch’s maximum power consumption is approximately 3.3W. Special cooling requirements may exist, depending upon the system environment. (Refer to the PEX 8606 Data Book for details). 10.1 Power Supplies The PEX 8606 has the following Power ball groups: VDD10 –... -
Page 25: Board-Level De-Coupling
0.0100 1.0V 0.0010 0.0001 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 Frequency - Hz Figure 15. Power Plane Impedance versus Frequency PEX 8606 Quick Start Hardware Design Guide – Version 1.2 Copyright © 2009 by PLX Technology, Inc. All rights reserved... -
Page 26: Figure 16. Capacitor Footprint Effects On Series Inductance
If holes do exist, capacitor values of some of the capacitors can be adjusted to fill them. PEX 8606 Quick Start Hardware Design Guide – Version 1.2 Copyright © 2009 by PLX Technology, Inc. All rights reserved... -
Page 27: References
PCI Express Card Electromechanical (CEM) Specification, Revisions 1.0a and 1.1 Right the First Time: A Practical Handbook on High Speed PCB and System Design , by Lee Ritchie PEX 8606 Quick Start Hardware Design Guide – Version 1.2 Copyright © 2009 by PLX Technology, Inc. All rights reserved...
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