Sai - CompuLab UCM-iMX93 Reference Manual

4.3.2

SAI

UCM-iMX93 supports up-to two of the i.MX93 integrated synchronous audio interface (SAI)
modules. The SAI module provides a synchronous audio interface (SAI) that supports full duplex
serial interfaces with frame synchronization, such as I2S, AC97, TDM, and codec/DSP interfaces.
The following main features are supported:

One transmitter with independent bit clock and frame sync supporting 1 data line. One
receiver with independent bit clock and frame sync supporting 1 data line.

Maximum Frame Size of 32 words.

Word size of between 8-bits and 32-bits. Separate word size configuration for the first
word and remaining words in the frame.

Asynchronous 32 × 32-bit FIFO for each transmit and receive channel
Please refer to the i.MX93 Reference manual for additional details. The tables below summarize
the SAI interface signals.
Table 9
Signal Name
SAI1_MCLK
SAI1_RX_DATA[0]
SAI1_TX_DATA[0]
SAI1_TX_DATA[1]
SAI1_TX_BCLK
SAI1_TX_SYNC
NOTE: SAI1 signals are multiplexed with other functions. For additional details please refer to
chapter 5.6 of this document.
Table 10
Signal Name
SAI2_MCLK
SAI2_RX_DATA[0]
SAI2_RX_DATA[1]
SAI2_RX_DATA[2]
SAI2_RX_DATA[3]
SAI2_RX_BCLK
Revised May 2023
SAI1 Signals
Pin # Type
Audio master clock. An input when
P1-19
IO generated externally and an output when
P1-45
generated internally.
Receive data, sampled synchronously by
P1-45 I
the bit clock
Transmit data signal synchronous to bit
P1-53 O
clock.
Transmit data signal synchronous to bit
P1-87 O
clock.
Transmit bit clock. An input when
P1-51 O generated externally and an output when
generated internally.
Transmit frame sync. An input sampled by
bit clock when generated externally. A bit
P1-87 O
clock synchronous output when generated
internally.
SAI2 Signals
Pin # Type
Audio master clock. An input when
P2-45 IO generated externally and an output when
generated internally.
Receive data, sampled synchronously by
P2-63 I
the bit clock
Receive data, sampled synchronously by
P2-65 I
the bit clock
Receive data, sampled synchronously by
P2-61 I
the bit clock
Receive data, sampled synchronously by
P2-59 I
the bit clock
Receive bit clock. An input when
P2-70 I generated externally and an output when
generated internally.
UCM-iMX93 Reference Guide
Voltage
Description
Domain
Voltage
Description
Domain
Peripheral Interfaces
Availability
3.3V Always
3.3V Always
3.3V Always
3.3V Always
3.3V Always
3.3V Always
3.3V Always
Availability
1.8V Always
1.8V Always
1.8V Always
1.8V Always
1.8V Always
1.8V Always
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