4.1
Display Interfaces
4.1.1
MIPI-DSI
The UCM-iMX93 MIPI-DSI interface is derived from the four-lane MIPI display interface available
on the i.MX93 SoC. The following main features are supported:
Compliant with MIPI DSI specification v1.2 and MIPI D-PHY specification v1.2
Maximum data rate per lane of 1.5 Gbps
Maximum resolution ranges up to 1920 x 1200 p60
The following table below summarizes the MIPI-DSI interface signals.
Table 5
Signal Name
DSI_CKN
DSI_CKP
DSI_DN0
DSI_DP0
DSI_DN1
DSI_DP1
DSI_DN2
DSI_DP2
DSI_DN3
DSI_DP3
4.1.2
LVDS Interface
UCM-iMX93 provides one LVDS interface derived from the i.MX93 LVDS display bridge. It
supports the following key features:
Single channel (4 lanes) output at up to 80MHz pixel clock
Resolutions of up to 1366 x 768 p60 or 1280 x 800 p60
The table below summarizes the LVDS interface signals.
Table 6
Signal Name
LVDS_CLK_N
LVDS_CLK_P
LVDS_D0_N
LVDS_D0_P
LVDS_D1_N
LVDS_D1_P
LVDS_D2_N
LVDS_D2_P
LVDS_D3_N
LVDS_D3_P
Revised May 2023
MIPI-DSI Interface Signals
Pin #
Type
P2-21
AO
Negative part of MIPI-DSI clock diff-pair
P2-23
AO
Positive part of MIPI-DSI clock diff-pair
P2-1
AO
Negative part of MIPI-DSI data diff-pair 0
P2-2
AO
Positive part of MIPI-DSI data diff-pair 0
P2-15
AO
Negative part of MIPI-DSI data diff-pair 1
P2-17
AO
Positive part of MIPI-DSI data diff-pair 1
P2-5
AO
Negative part of MIPI-DSI data diff-pair 2
P2-7
AO
Positive part of MIPI-DSI data diff-pair 2
P2-11
AO
Negative part of MIPI-DSI data diff-pair 3
P2-13
AO
Positive part of MIPI-DSI data diff-pair 3
LVDS Interface Signals
Pin #
Type
P2-14
AO
P2-12
AO
P2-26
AO
P2-24
AO
P2-20
AO
P2-18
AO
P2-8
AO
P2-6
AO
P2-4
AO
P2-2
AO
UCM-iMX93 Reference Guide
Description
Description
Negative part of LVDS clock diff-pair
Positive part of LVDS clock diff-pair
Negative part of LVDS data diff-pair 0
Positive part of LVDS data diff-pair 0
Negative part of LVDS data diff-pair 1
Positive part of LVDS data diff-pair 1
Negative part of LVDS data diff-pair 2
Positive part of LVDS data diff-pair 2
Negative part of LVDS data diff-pair 3
Positive part of LVDS data diff-pair 3
Peripheral Interfaces
Availability
Always
Always
Always
Always
Always
Always
Always
Always
Always
Always
Availability
Always
Always
Always
Always
Always
Always
Always
Always
Always
Always
12
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