Advertisement
49
IGP1
52
IGPV
53
IGPH
54~57,59~62
IPD0~IPD7
64~67,69~72
HPD0~HPD7
80
XTRI
81,82,84,85,
XPD0~XPD7
89,90,86,87
91
XRV
92
XRH
94
XCLK
95
XDQ
96
XRDY
97
TRSTN
98
TCK
99
TMS
UOC (
Ⅲ TDA15063H)：
The UOCIII series combines the functions of a Video Signal Processor (VSP) together with a FLASH
embedded TEXT/Control/Graphics -Controller (TCG -Controller) and US Closed Caption decoder.
Main Features:
●DVB/VSB IF circuit for preprocessing of digital TV signals;
●Video switch with 3 external CVBS inputs and a CVBS output;
●Automatic Y/C signal detector;
●Adaptive digital (4H/2H) PAL/NTSC comb filter for optimum separation of the luminance and the
chrominance signal;
●Picture improvement features with peaking (with switchable center frequency, depeaking, variable
positive/negative peak ratio, variable pre-/overshoot ratio and video dependent coring), dynamic skin tone
control, gamma control and blue and black stretching. All features are available for CVBS, Y/C and
RGB/YPBPR signals.
All manuals and user guides at all-guides.com
general purpose output signal 0; image-port (controlled by subaddr.
"84","85")
general purpose output signal 1; image-port (controlled by subaddr.
"84","85"),
same functions as IGP0
multi purpose vertical reference output signal; image-port
(controlled by subaddr. "84","85")
multi purpose horizontal reference output signal; image-port
(controlled by subaddr. "84","85")
image port data output
Host port data I/O, carries UV chrominance information in 16 bit video
I/O modes
X-port output control signal, effects all X-port pins (XPD[7:0], XRH,
XRV, XDQ
and XCLK) enable and active polarity is under software control (bits
XPE in subaddr. "83")
expansion-port data
expansion-port data
vertical reference I/O expansion-port:
In ten bit video output mode: this signal represents the video bit 0.
horizontal reference I/O expansion-port:
In ten bit video output mode: this signal represents the video bit 1.
clock I/O expansion port
data qualifier I/O expansion port
task flag or read signal from scaler, controlled by XRQT (subaddr.
83H)
Test ReSeT Not for Boundary Scan Test (with internal pull-up); for
board design
without Boundary Scan connect TRSTN to 'ground'(1)
Test Clock for Boundary Scan Test (with internal pull-up)
Test Mode Select for Boundary Scan Test or Scan Test (with internal pull-up)
(2)
(2)
21
Advertisement
