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4,14,22,30
OGND
38,46,165
7，8，9，10，
VPA0~VPA7
15，16，17，18
11,116,130,132
VDDC
12,117,159
CGND
23~28,31,32
VPB0~VPB7
35,36,39~44
VPC0~VPC7
47,53,57,58,55
AGND
60,66,70,71,75
81,83,85,86,
48,54,59,61,67
VDDA
69,76,82,85,87,88
49
REFB/Pb
52,51,50
B/Pb1~ B/Pb3
56
BIAS
62
REFG/Y
65,64,63
G/Y1~G/Y3
74,73,72
SOG/Y1~SOG/Y3
77
REFR/Pr
80,79,78
R/Pr1~ R/Pr3
89~92,97~101
TST0~TST17
112,121,122,
124,125,160~163
93
PD
94
OE
96
A0
102
COAST
103
GAIN
104
CLAMP
105~107
VSYNC1~VSYNC3 Vertical synchronization input
108~110
H(C)SYNC1~
H(C)SYNC3
111
CKEXT
113
TCLK
114
DIS
118
SDA
119
SCL
120,126,127,131
IGND
133,142,148,
123,138,139,145
VDDI
151,157
166
PL
167
DE
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Video
ground
Video port A
Power supply port
Ground
Video port B
Video port C
Analog ground
Power supply port
Blue/blue-chrominance channel reference input
Blue/blue-chrominance channel analog input
Bias input
Green/green-chrominance
input
Green/green-chrominance channel analog input
Sync on green//brightness channel input
Red/red-chrominance channel reference input
Red/red-chrominance channel analog input
Reserved for test
Power-down control input
Output enable input
I²C bus address control input
PLL control input
Gain input
Clamp input
Horizontal (composite)synchronization input
External clock input
Reserved for test
I²C bus disable control input
I²C bus data input/output
I²C bus clock input
Input digital ground
Input digital supply voltage
PLL disable belock output
Data enable output
port
output
channel
reference
14
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