Marantz SR8001 Service Manual page 131

IC62 : ADV7401BS80
Pin No.
4
99
98
81, 19
82, 16
80
78
36
38
37
46
70
59
15
64
65
61, 62
68, 69
67
86
85
79
35
52
77
Mnemonic Type
HS/CS O
VS O
FIELD/DE O
SDA1, SDA2 I/O
SCLK1, SCLK2 I
ALSB I
I
RESET
LLC1 O
XTAL I
XTAL1 O
ELPF O
TEST0
TEST1 O
SFL/SYNC_OUT O
REFOUT O
CML O
CAPY1 to CAPY2 I
CAPC1 to CAPC2 I
BIAS O
HS_IN/CS_IN I
VS_IN I
DE_IN I
DCLK_IN I
SOG I
SOY I
Function
HS is a Horizontal Synchronization Output Signal (SDP and CP modes).
CS is a Digital Composite Synchronization Signal (and can be selected
while in CP mode).
Vertical Synchronization Output Signal (SDP and CP modes).
Field Synchronization Output Signal (all interlaced video modes). This
pin also can be enabled as a Data Enable signal (DE) in CP mode to allow
direct connection to a HDMI/DVI Tx IC.
2
I C Port Serial Data Input/Output Pins. SDA1 is the data line for the
Control port and SDA2 is the data line for the VBI readback port.
2
I C port serial clock input (max clock rate of 400 kHz). SCLK1 is the clock
line for the Control port and SCLK2 is the clock line for the VBI data
readback port.
2
This pin selects the I C address for the ADV7401 Control and VBI
readback ports. ALSB set to a logic 0 sets the address for a write to
control port of 0x40 and the readback address for the VBI port of 0x21.
ALSB set to a logic high sets the address for a write to control port of
0x42 and the readback address for the VBI port of 0x23.
System reset input, active low. A minimum low reset pulse width of 5 ms
is required to reset the ADV7401 circuitry.
LLC1 is a line locked output clock for the pixel data (range is 12.825 MHz
to 140 MHz for ADV7401KSTZ-140; 12.825 MHz to 110 MHz for
ADV7401BSTZ-110; 12.825 MHz to 80 MHz for ADV7401BSTZ-80).
Input pin for 28.6363 MHz crystal, or can be overdriven by an external
3.3 V 28.6363 MHz clock oscillator source to clock the ADV7401.
This pin should be connected to the 28.6363 MHz crystal or left as a no
connect if an external 3.3 V 28.6363 MHz clock oscillator source is used
to clock the ADV7401. In crystal mode the crystal must be a fundamental
crystal.
The recommend external loop filter must be connected to this ELPF pin.
This pin should be left unconnected or alternatively tied to AGND.
This pin should be left unconnected.
Subcarrier Frequency Lock (SFL ). This pin contains a serial output stream
which can be used to lock the subcarrier frequency when this decoder is
connected to any Analog Devices digital video encoder. SYNC_OUT is
the sliced sync output signal only available in CP mode.
Internal Voltage Reference Output.
Common-Mode Level Pin (CML)for the internal ADCs.
ADC Capacitor Network.
ADC Capacitor Network.
External Bias Setting Pin. Connect the recommended resistor (1.35kΩ)
between pin and ground.
Can be configured in CP mode to be either a digital HS input signal or a
digital CS input signal used to extract timing in a 5-wire or 4-wire RGB
mode.
VS input signal. Used in CP mode for 5-wire timing mode.
Data Enable Input Signal. Used in 24-bit digital input port mode (for
example, processing 24-bit RGB data from a DVI Rx IC).
Clock Input Signal. Used in 24-bit digital input mode (for example,
processing 24-bit RGB data from a DVI Rx IC) and also in digital CVBS
input mode.
Sync on Green Input. Used in embedded sync mode.
Sync on Luma Input. Used in embedded sync mode.
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