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XC-1 Hardware Manual (1.3.2)
11.1 I/O Port-to-Pin Mapping
The table below provides a full description of the port-to-pin mappings described
throughout this document.
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Pin
Port
1b
4b
8b
XnD0
P1A0
XnD1
P1B0
XnD2
P4A0 P8A0 P16A0
XnD3
P4A1 P8A1 P16A1
XnD4
P4B0
P8A2 P16A2
XnD5
P4B1
P8A3 P16A3
XnD6
P4B2
P8A4 P16A4
XnD7
P4B3
P8A5 P16A5
XnD8
P4A2 P8A6 P16A6
XnD9
P4A3 P8A7 P16A7
XnD10
P1C0
XnD11
P1D0
XnD12
P1E0
XnD13
P1F0
XnD14
P4C0 P8B0
XnD15
P4C1 P8B1
XnD16
P4D0 P8B2
XnD17
P4D1 P8B3
XnD18
P4D2 P8B4
XnD19
P4D3 P8B5
XnD20
P4C2 P8B6
XnD21
P4C3 P8B7
XnD22
P1G0
XnD23
P1H0
XnD24
P1I0
XnD25
P1J0
XnD26
P4E0
P8C0 P16B0
XnD27
P4E1
P8C1 P16B1
XnD28
P4F0
P8C2 P16B2
XnD29
P4F1
P8C3 P16B3
XnD30
P4F2
P8C4 P16B4
XnD31
P4F3
P8C5 P16B5
XnD32
P4E2
P8C6 P16B6
XnD33
P4E3
P8C7 P16B7
XnD34
P1K0
XnD35
P1L0
XnD36
P1M0
P8D0 P16B8
XnD37
P1N0
P8D1 P16B9
XnD38
P1O0
P8D2 P16B10
XnD39
P1P0
P8D3 P16B11
XnD40
P8D4 P16B12
XnD41
P8D5 P16B13
XnD42
P8D6 P16B14
XnD43
P8D7 P16B15
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Processor
16b
0
PROTOTYPE_AREA_0
PROTOTYPE_AREA_1
PORT_CLOCKLED_0 [IIII]
PORT_CLOCKLED_0 [V]
PORT_CLOCKLED_1 [VIII]
PORT_CLOCKLED_1 [IX]
PORT_CLOCKLED_1 [X]
PORT_CLOCKLED_1 [XI]
PORT_CLOCKLED_0 [VI]
PORT_CLOCKLED_0 [VII]
PROTOTYPE_AREA_2
PROTOTYPE_AREA_3
PORT_CLOCKLED_SELG
PORT_CLOCKLED_SELR
P16A8
PORT_CLOCKLED_2 [XII]
P16A9
PORT_CLOCKLED_2 [I]
P16A10
PORT_BUTTON [A]
P16A11
PORT_BUTTON [B]
P16A12
PORT_BUTTON [C]
P16A13
PORT_BUTTON [D]
P16A14
PORT_CLOCKLED_2 [II]
P16A15
PORT_CLOCKLED_2 [III]
RESERVED
PORT_UART_TX
PORT_UART_RX
RESERVED
PROTOTYPE_AREA_4
PROTOTYPE_AREA_5
PROTOTYPE_AREA_6
PROTOTYPE_AREA_7
PROTOTYPE_AREA_8
PROTOTYPE_AREA_9
PROTOTYPE_AREA_10
PROTOTYPE_AREA_11
PORT_SPEAKER
RESERVED
PROTOTYPE_AREA_12
PROTOTYPE_AREA_13
PROTOTYPE_AREA_14
PROTOTYPE_AREA_15
PORT_BUTTONLED [A]
PORT_BUTTONLED [B]
PORT_BUTTONLED [C]
PORT_BUTTONLED [D]
15/17
2
X2PortA
Header
X2PortB
Header
X2PortC
Header
X2PortD
Header
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