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4.6
Advanced Chipset Setup
This section allows you to configure the system based on the specific
features of the installed chipset. This chipset manages bus speeds and
the access to the system memory resources, such as DRAM and the
external cache. It also coordinates the communications between the
conventional ISA and PCI buses. It must be stated that these items
should never be altered. The default settings have been chosen
because they provide the best operating conditions for your system.
You might consider and make any changes only if you discover that the
data has been lost while using your system.
Phoenix – AwardBIOS CMOS Setup Utility
Advanced Chipset Features
DRAM Timing Selectable
X CAS Latency Time
X Active to Precharge Delay
X DRAM RAS# to CAS# Delay
X DRAM RAS# Precharge
DRAM Data Integrity Mode
MGM Core Frequency
System BIOS Cacheable
Video BIOS Cacheable
Memory Hole At 15M-16M
Delayed Transaction
Delay Prior to Thermal
AGP Aperture Size (MB)
** ON-Chip VGA Setting **
On-Chip VGA
On-Chip Frame Buffer size
Boot Display
Panel Number
Move Enter: Select + / - /PU/PD: Value F10: Save ESC: Quit F1: General Help
F5: Previous Values
F6: Fail-Safe Defaults
NOTE:
Panel Number: 1 (Default Panel 1: TOSHIBA LTM10C348F)
26
Item Help
By SPD
Menu Level
2.5
7
3
3
Non-ECC
Auto Max 266MHz
Enabled
Disabled
Disabled
Enabled
16Min.
64
Enabled
32MB
VBIOS Default
1
F7: Optimized Defaults
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