Analog Devices AD6122 Manual page 18

AD6122
J2
0
VPOS
2.9V – 4.2V
VREG OUT
C1
X2
10nF
0
LOIPP
X1 X3
X5
100nH
1:8
TXOP
X6
3pF
X4
T1
PD1
PD1
PD2
PD2
FMMT4403CT-ND
LDOE
Q1 LDOB
J1
LDOC
C23
18pF
LDOGND
DGND
LOIPP
C2
VCC
10nF
C24
LOIPN
0.1 F
DVCC
DVCC
L2
C3
X8
220nH
10nF
0
TXOPP
X9
X7
TXOPN
X10
C4
TXVCC
TXVCC
0
10nF
L3
220nH
IFGND
VCC
C25
10nF
Figure 33. Schematic Diagram of the Evaluation Board
AD6122
R12
0
VGAIN
C28
10nF
REFIN
REFOUT
C29
10nF
IFVCC
IFVCC
IFGND
IIPP
IIPP
IIPN IIPN
MODCMREF MODCMREF
QIPN QIPN
QIPP QIPP
MODOPP
C8
10nF
MODOPN
C10
10nF
X11
IFINP
0
IFINN
C11
10nF
R14 = 442
R14
R15 = 100
R16 = 442
X18
0
–18–
VGAIN
REFOUT
VREG OUT VREG OUT
C26
C27
10nF
10nF
L4
L5
180nH
180nH
X16
100nH
8:1
X12 X15
C9
X13 4pF
10nF
T2
X14
L6
X25
0
C30
R13
R16
R15
X23
27nH
X19
8:1
X22
X26
X20
56nH
0
T3
X21
MODOP
X17
IFIP
X24
REV. B