CML Microcircuits CMX7031 Application Note page 24

Application Note
5.6 STATE 6: Voice Rx
At this point, the CMX7031 has detected a CTCSS tone that matches the CTCSS address
programmed into the AUDIO CONTROL ($C2) register. This means that the incoming transmission is
a voice call intended for the radio's user. The following register manipulations will configure the
CMX7031 to process the incoming voice call and present it to the Audio Output pin.
Register
Register Name
Address
$B1 INPUT GAIN and OUTPUT
SIGNAL ROUTING
$C0 POWER DOWN CONTROL
$B0 ANALOGUE OUTPUT GAIN
$CE INTERRUPT MASK
$C1 MODE CONTROL
5.7 STATE 7: FFSK / MSK Rx
At this point, the CMX7031 has detected the presence of RF carrier and 2400 bps FFSK / MSK
signals. The CMX7031 is configured to receive this FFSK / MSK message as follows:
Register
Register Name
Address
$B6 MODEM ADDRESS
$CE INTERRUPT MASK
$C1 MODE CONTROL
A timer should be started to prevent the CMX7031 from continuously searching for a Frame Head
should an error condition occur.
The CMX7031 will check the incoming Frame Head for a valid Checksum A, and if found, will then
compare the address in Control Field byte 1 to the user programmed address in the Modem Address
($B6) register. (The CMX7031 will also check for a "40" FFSK / MSK address.) The CMX7031 will
set b5 of the Status register and issue an interrupt if Checksum A indicates correct Frame Head bytes
and if the FFSK / MSK addresses match. The host microcontroller can read out the address and
size / information bytes from Rx Data # 1 register ($C5), and optionally, the Control byte and Frame
Head Checksum A byte from Rx Data # 2 register ($C9).
The CMX7031 will then issue interrupts when new data is ready for host processing. The four
available received data bytes can be read out of Rx Data # 1 and # 2 ($C5 and $C9) registers. The
host microcontroller has approximately 20ms to read out the new data after the interrupt has been
issued; otherwise, new incoming data will overwrite the old data.
Status register ($C6) b7,6 = 11 when the last byte of the data frame has been received. When b7 = 1
is detected, the firmware should revert to STATE 3, Sleep.
© 2007 CML Microsystems PLC
Register
Contents
0x0050
0x38D0
0x000F
0x8B02
0x4041
Table 12: STATE 6 Register Settings
Register
Contents
0x4F00
0x83F2
0x0009
Table 13: STATE 7 Register Settings
24 of 28
CMX7031
: An Example Core Design for a Complete Family Radio
Effect
Input 1 gain = 0dB, Input 1 source = Disc, Audio Output =
Output 1 (Rx signal processing path).
Enabled: Disc amp, Input 1, Output 1, Audio output, Bias
block, crystal oscillator circuit. Programming Register
contents protected.
Audio output attenuation = 0dB.
Enabled interrupts: CTCSS, AUXADC1, AUXADC2, RF
status change.
Audio source = Input 1, audio processing path enabled,
subaudio source = Input 1, CTCSS detection enabled,
Rx mode.
Effect
Address 79d programmed.
Enabled interrupts: AUXADC1, AUXADC2, FFSK / MSK
data complete, data ready, data CRC, 2400 bps, RF
status change.
Subaudio source = Input 1, FFSK / MSK source = Input
1, 2400 bps enabled, Rx mode.
AN/2WR/7031/FRS/3 July 2007