CML Microcircuits CMX7031 Application Note page 20

Application Note
Register
Register Name
Address
$AB SYSTEM CLK 1 PLL
$AC SYSTEM CLK 1 REF
$AD SYSTEM CLK 2 PLL
$AE SYSTEM CLK 2 REF
$B2 RF CHANNEL DATA
$B2 RF CHANNEL DATA
$B2 RF CHANNEL DATA
$B2 RF CHANNEL DATA
$B2 RF CHANNEL DATA
$B2 RF CHANNEL DATA
$B2 RF CHANNEL DATA
$B2 RF CHANNEL DATA
$C8 PROGRAMMING REGISTER (P1.0)
$C8 PROGRAMMING REGISTER (P1.1)
$C8 PROGRAMMING REGISTER (P2.0)
$C8 PROGRAMMING REGISTER (P2.1)
$C8 PROGRAMMING REGISTER (P2.2)
$C8 PROGRAMMING REGISTER (P2.3)
$C8 PROGRAMMING REGISTER (P2.4)
$C8 PROGRAMMING REGISTER (P2.5)
$C8 PROGRAMMING REGISTER (P3.0)
$C8 PROGRAMMING REGISTER (P3.1)
$C8 PROGRAMMING REGISTER (P3.2)
$C8 PROGRAMMING REGISTER (P3.3)
$C8 PROGRAMMING REGISTER (P3.4)
$C8 PROGRAMMING REGISTER (P3.5)
$C8 PROGRAMMING REGISTER (P3.6)
$C8 PROGRAMMING REGISTER (P3.7)
$C8 PROGRAMMING REGISTER (P4.0)
$C8 PROGRAMMING REGISTER (P4.1)
$C8 PROGRAMMING REGISTER (P4.2)
$C8 PROGRAMMING REGISTER (P4.3)
$C8 PROGRAMMING REGISTER (P4.4)
$C8 PROGRAMMING REGISTER (P4.5)
$C8 PROGRAMMING REGISTER (P4.6)
$C8 PROGRAMMING REGISTER (P4.7)
$C8 PROGRAMMING REGISTER (P4.8)
$C8 PROGRAMMING REGISTER (P4.9)
$A8 AUXDAC CONTROL / DATA
© 2007 CML Microsystems PLC
Register
Contents
0x1200
0xE0C8
0x0E00
0xE0C8
0x408D
0x4424
0x4A00
0x4C01
0x71BC
0x7405
0x7A00
0x7C01
0xD6D6
0x50D9
0xE278
0x60B8
0x6000
0x6000
0x6000
0x6F00
0xF000
0x7000
0x7018
0x7099
0x70C8
0x7200
0x7140
0x7008
0x8000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x1CB4
0x0000
0x004B
0x8974
Table 8: STATE 2 Register Settings
20 of 28
CMX7031
: An Example Core Design for a Complete Family Radio
Effect
SysClk1 VCO output divider = 4, SysClk1 PLL divider =
512
SysClk1 source = SysClk1 PLL, SysClk1 PLL enabled,
normal O / P slew, reference divider = 200.
SysClk2 VCO output divider = 3, SysClk2 PLL divider =
512
SysClk2 source = SysClk2 PLL, SysClk2 PLL enabled,
normal O / P slew, reference divider = 200.
Channel 1 Tx configured for 462.5625MHz.
Channel 2 Rx configured for 392.5625MHz.
Transmitted FFSK / MSK and ring tone level =
500mV .
RMS
50mV FFSK / MSK detection threshold, inband
RMS
detection bandwidth +/-1.3% (will decode).
Transmitted CTCSS tone level = 45mV
CTCSS detection threshold 25mV
bandwidth +/-1.1% (will decode).
Write to this register to access other Block 2 registers.
CTCSS drop out time = 120ms. (This represents the
length of time the CTCSS tone can drop out before loss
of CTCSS is asserted. The setting of this register also
determines the deresponse time, which is typically 90ms
longer than the programmed drop out time.)
P3.0 = 0 (default ADC1 averaging length).
P3.1 = 0 (default ADC2 averaging length).
These writes configure the CMX7031 to use the
19.2MHz TCXO as its main clock source.
Write to this register to access other Block 4 registers.
Tx Limiter set for limiting at 1.48V
Write to this register to access other Block 4 registers.
Preferred order for audio signal processing blocks.
DAC3 enabled and generating 1.2V signal for TCXO
control signal.
AN/2WR/7031/FRS/3 July 2007
.
RMS
, CTCSS detection
RMS
(525mV )
PP RMS