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CML Microcircuits CMX7031 Application Note page 15

Example core design for a complete family radio

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Application Note
The Input 1 or Input 2 gain stages can provide from 0dB to 22.4dB of gain. (Gain settings are
adjusted in the Input Gain and Output Signal Routing ($B1) register.) For the purposes of this
example, the external components surrounding the CMX7031 input amplifier are configured for unity
gain. Therefore, the input level for the Input 1 or 2 internal amplifier is as follows:
If Input 1 or 2 gain = 0dB, the input to Input 1 or 2 amplifier = 231mV
If Input 1 or 2 gain = 22.4dB, the input to Input 1 or 2 amplifier ≅ 18mV
The gain stages, both internal and external, can be adjusted for various input signals so long as these
figures are not exceeded. The following figure illustrates the transmit signal path with the previously
calculated signal levels:
231mV
152mV
RMS
RMS
Pre-
Compressor
Emphasis
MIC F/B
MIC I/P
V
BIAS
18mV
(if $B1 Input 1 gain = +22.4dB)
RMS
OR
231mV
(if $B1 Input 1 gain = 0dB)
RMS
4.6.2
Tx Limiter Calculations
The Tx soft limiter threshold (centered on AV
Programming Block P4.7. The programmed value required for 525mV
as follows:
Bit resolution = AV
Desired limiting threshold = 525mV
Number of bits for desired limiting threshold = 1.48 V
7348d = 0x1CB4
Since the two uppermost bits of P4.7 are zeros, a value of 0x1CB4 loaded into P4.7 will cause Tx
limiting to occur at 525mV
© 2007 CML Microsystems PLC
455mV
RMS
300Hz
Scrambler
Filter
Input 1
Analog
Routing
Figure 4: Transmit Audio Signal Level Example
(with preferred signal processing path)
DD
/ 16384 = 3.3V / 16384 = 201μV / bit
DD
signal level, centered on AV
RMS
15 of 28
CMX7031
: An Example Core Design for a Complete Family Radio
45mVrms
CTCSS
Mux
Routing
Voice Filter &
Mux
Soft Limiter
455mV
RMS
/ 2) is determined by the value loaded into
= 1.48V
RMS
PP
PP
/ 2.
DD
.
RMS
.
RMS
MOD 1 O/P
0dB
Analog
limiting can be determined
RMS
/ (201μV / bit) ≅ 7348 bits
AN/2WR/7031/FRS/3 July 2007
500mV
RMS
Total
Output

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