CML Microcircuits CMX7031 Application Note page 21

Application Note
5.3 STATE 3: Sleep
This is the default operating state for the CMX7031 in this application.
In this condition, the CMX7031 is in idle mode and powered down to the maximum extent possible
while monitoring for incoming carrier.
Highlights of STATE 3 are as follows:
•
Channel 2 Synthesizer placed in Rx mode.
•
DAC1 is disabled (this deactivates RAMDAC function used by Tx states).
•
Received Signal Strength Indicator (RSSI) signal is monitored by ADC1 via AUXADC1 input
pin.
•
Battery voltage is monitored by ADC2 via AUXADC4 input pin.
•
TCXO control signal provided on AUXDAC3 output pin.
•
CMX7031 is powersaved to maximum extent possible.
•
Device is placed into idle mode.
The following register configuration will achieve the previously stated objectives:
Register
Register Name
Address
$B3 RF CHANNEL CONTROL
$A8 AUXDAC CONTROL / DATA
$B5 AUXADC THRESHOLD
$B5 AUXADC THRESHOLD
$B5 AUXADC THRESHOLD
$A7 AUXADC / TX MODE
$C0 POWER DOWN CONTROL
$CE INTERRUPT MASK
$C1 MODE CONTROL
Possible subsequent states from STATE 3 include:
•
STATE 4: RX Startup
This will occur if an incoming carrier signal causes the RSSI signal to exceed the
o
ADC1 high threshold level.
•
STATE 5: Ring Tone Tx
This will occur if the user presses a button on the radio.
o
© 2007 CML Microsystems PLC
Register
Contents
0x0500
0x0000
0x423E
0x0117
0xC1BE
0x07B0
0x0050
0x8300
0x0000
Table 9: STATE 3 Register Settings
21 of 28
CMX7031
: An Example Core Design for a Complete Family Radio
Effect
RF synth clk = reference clk. Channel 2: 1 cycle phase
lock tolerance, + charge polarity, low charge pump gain,
Rx mode enabled. Channel 1: powersaved.
Disable DAC1 (this is done because Tx states, which
use DAC1's RAMDAC function, transition to this state
once complete.)
ADC1 high threshold = 1.85V (RSSI high).
ADC1 low threshold = 0.9V (RSSI low).
ADC2 high threshold = 1.44V (corresponds to "low
battery warning" of 3.6V).
ADC1 input from AUXADC1 input pin (RSSI), rolling
averaging. ADC2 input from AUXADC4 input pin
(battery voltage), rolling averaging.
NOTE: Default averaging values in Program Block P3.0
and P3.1 result in 50% averaging.
Bias block enabled, Programming Register contents
protected.
AUXADC1 and AUXADC2 IRQ enabled.
Idle mode.
AN/2WR/7031/FRS/3 July 2007