CML Microcircuits CMX7031 Application Note page 12

Application Note
to RF Synthesiser
Ref Clk selection
÷200
96kHz
÷1 to 512
$AC
b8..0
÷200
96kHz
÷1 to 512
$AE
b8..0
osc
19.2MHz
from TCXO
Figure 3: Example Configuration for System Clock Generators
Register
$AB System Clk 1 PLL
$AC System Clk 1 Ref
$AD System Clk 2 PLL
$AE System Clk 2 Ref
Table 5: Example Settings for System Clock Generators
This example application uses an external 19.2MHz TCXO to derive the system clock outputs and the
CMX7031 main clock signal. Since the external TCXO frequency is not the default 6.144MHz value,
adjustments to Programming Register blocks P3.2 through P3.7 are required to ensure proper
operation. These adjustments are described in the section for STATE 2, Setup.
The CBUS registers $BC and $BD (for "MainClk" derivation) are controlled automatically by the
Function Image™ and must not be accessed by the user. Please consult Section 6.13.2 of the
CMX7031 data sheet for more information.
© 2007 CML Microsystems PLC
÷512
49.152M Hz
96kHz
÷1 to 1024
P D
$AB
b9..0
÷512
96kHz
49.152M Hz
÷1 to 1024
P D
$AD
b9..0
MainClk VCO Output
(49.152MHz typ.)
Contents
0x1200
0xE0C8
0x0E00
0xE0C8
12 of 28
CMX7031
: An Example Core Design for a Complete Family Radio
VCO
$AC
VCO
$AE
Comments
SysClk1 VCO output divider = 4, SysClk1 PLL divider = 512
SysClk1 source = SysClk1 PLL, SysClk1 PLL enabled, normal
O / P slew, reference divider = 200.
SysClk2 VCO output divider = 3, SysClk2 PLL divider = 512
SysClk2 source = SysClk2 PLL, SysClk2 PLL enabled, normal
O / P slew, reference divider = 200.
÷4
12.288MHz
÷1 to 64
System
Clock 1
$AB
b15..10
÷3
16.384MHz
÷1 to 64
System
Clock 2
$AD
b15..10
AN/2WR/7031/FRS/3 July 2007