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3.3.2. Block Description
CALYPSO architecture is based on two processor cores ARM7 and DSP using the generic RHEA bus
standard as interface with their associated application peripherals.
CALYPSO is composed from the following blocks:
• ARM7TDMIE : ARM7TDMI CPU core
• DSP subchip
• ARM peripherals:
General purpose peripherals
• ARM Memory Interface for external RAM, Flash or ROM
• 4 Mbit Static RAM with write-buffer
Application peripherals
• ARM General purposes I/O with keyboard interface and two PWM modulation signals
• UART 16C750 interface (UART_IRDA) with
→ IRDA control capabilities (SIR)
→ Software flow control (UART mode).
• UART 16C750 interface (UART_MODEM) with
→ Hardware flow protocol (DCD, CTS/RTS)
→ Autobaud function
• SIM Interface.
• TPU(Time Processing Unit) : Processing for GSM time base
• TSP(Time Serial Port) : GSM data interface with RF and ABB
Memory Interface : External/Internal Memory Interface
nCS0 : FLASH1, 16bit access, 3 wait state
nCS1 : FLAHS2, 16bit access, 3 wait state
nCS2 : Ext SRAM, 16bit access, 3 wait state
nCS3 : Main LCD(16bit access), OEL(8bit access) addressing, 3 wait state
nCS4 : MIDI(8bit access), USB(8bit access) addressing, 3 wait state
nCS6 : Int SRAM, 32bit access, 0 wait state
* Calypso is internally 39MHz machine (25ns machine cycle), so it requires 3 wait-state for 80ns
access(25*4 = 100 ns).
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