LG G5500 Manual page 14

3.2.2. IF
A quadrate image-rejection mixer downconverts the RF signal to a 100kHz intermediate frequency (IF)
with the RFLO from the Si4133T-BM[U505]. The RFLO frequency is between 1849.8 and 1918.8 MHz,
and is divided by two in the Si4200 for EGSM modes. The RFLO frequency is between 1804.9 and
1879.9 MHz, and is divided by one in the Si4200 for DCS modes. The mixer output is amplified with
an analog programmable gain amplifier (PGA), which is controlled with the AGAIN[2:0] bits in register
05h.
The quadrate IF signal is digitized with high resolution A/D converters (ADCs).
The Si4201-BM[U503] down-converts the ADC output to baseband with a digital 100kHz quadrate LO
signal. Digital decimation and IIR filters perform channel selection to remove blocking and reference
interference signals. The response of the IIR filter is programmable to a high selectivity
setting(CSEL=0) or a low selectivity setting (CSEL=1). After channel selection, the digital output is
scaled with digital PGA, which is controlled with the DGAIN[5:0] bits in register 05h.
3.2.3. Demodulator and Baseband Processing
The amplified digital output signal go through with DACs that drive a differential analog signal onto the
RXIP, RXIN, RXQP and RXQN pins to interface to standard analog ADC input baseband ICs.
No special processing is required in the baseband for offset compensation or extended dynamic range.
Compared to a direct-conversion architecture, the low-IF architecture has a much greater degree of
immunity to dc offsets that can arise from RF local oscillator(RFLO) self-mixing, 2nd order distortion of
blockers, and device 1/f noise.
3.2.4. Synthesizer Part
The synthesizer IC, the Si4133T-BM[U505] is a monolithic CMOS integrated circuit that performs IF
and RF synthesis. Two complete PLLs are integrated including VCOs, varactors, resonators, loop
filters, reference and VCO dividers, and phase detectors. Differential outputs for the IF and RF PLLs
are provided for direct connection to the Si4200-BM[U502] transceiver IC. The RF PLL uses two
multiplexed VCOs.
The RF1 VCO is used for Receive mode, and the RF2 VCO is used for Transmit mode. The IF PLL is
used only during Transmit mode and uses a single VCO. The center frequency of each of the three
VCOs on the Si4133T is set by connection of an external inductance(Lext). The IF and RF output
frequencies are set by programming the N-Divider registers, N[RF1], N[RF2] and N[IF]. Programming
the N-Divider register for either RF1 or RF2 automatically selects the proper VCO. The output
frequency of each PLL is as follows:
A programmable divider at the XIN pin allows either a 13 or 26MHz from the external applied crystal
oscillator. The RF PLL phase detector update rate(fø) can be programmed with the RFUP bit in
register 31h to either fø = 100kHz or fø= 200kHz. The IF PLL always uses fø = 200kHz. Receive
mode should use fø = 100kHz in DCS1800 and PCS1900 bands, and fø = 200kHz in the GSM850 and
E-GSM 900 bands.
fout = N * fø
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