American Megatrends 43 Series User Manual page 60

ADVANCED CHIPSET SETUP Options,
Continued
DMA Clock Select
Allows the user to program the DMA clock to operate at either BCLK or BCLK/2 (BUS CLOCK). The BIOS and Power-On defaults are BCLK/2.
Refresh Command Width
This option specifies the command width during a refresh cycle. These pulse widths are derived from the oscillator. The settings are 140 ns, 210 ns, 280 ns, or
350 ns. The BIOS Default is 280 ns. The Power-On Default is 350 ns.
Coprocessor Ready Controlled By
This option determines whether READY is controlled by the C&T SCATSX (82C836) or the math coprocessor (80387SX) during coprocessor accesses. Settings
are 80387SX generates READY or 82C836 generates READY. The BIOS and Power-On defaults are 80387SX generates READY.
Additional RAM Wait State
Allows an additional T-state (two PROCLK cycles) to be inserted on all local memory accesses. The added T-state is added during the CAS (Column Address
Strobe) active interval, extending the width of the CAS pulse. Settings are Enabled or Disabled. The defaults are Enabled.
RAS Timeout Feature
A RAS (Row Address Strobe) Timeout Feature is provided to support DRAMs that require a 10 microsecond maximum on RAS-active time. If the timeout is
enabled, RAS is not allowed to remain low continuously for more than 9.5 microseconds. If the timeout is disabled, periodic refresh cycles limit the maximum
possible RAS active time to 15 microseconds. Settings are Enabled or Disabled. The BIOS and Power-On Defaults are Disabled.