Philips 55PFL6900/F7 Service Manual page 136

Digital Main 10 Schematic Diagram [TYPE B]
1 NOTE:
The order of pins shown in this diagram is different from that of actual IC3001.
IC3001 is divided into nine and shown as IC3001 (1/9) ~ IC3001 (9/9) in this Digital Main Schematic Diagram Section.
CONTINUE
DIGITAL 9
P-ON+5V
P-ON+3.3V
TO LCD PANEL
ASSEMBLY CN3901
GND 1
C3916 0.1
RX7(+) 2
C3915 0.1
RX7(-) 3
4
GND 4
C3914 0.1
RX6(+) 5
C3913 0.1
RX6(-) 6
GND 7
C3912 0.1
RX5(+) 8
C3911 0.1
RX5(-) 9
GND 10
C3910 0.1
RX4(+) 11
C3909 0.1
RX4(-) 12
GND 13
C3908 0.1
RX3(+) 14
C3907 0.1
RX3(-) 15
GND 16
C3906 0.1
RX2(+) 17
C3905 0.1
RX2(-) 18
GND 19
C3904 0.1
RX1(+) 20
C3903 0.1
RX1(-) 21
GND 22
C3902 0.1
RX0(+) 23
C3901 0.1
RX0(-) 24
GND 25
LOCKN 26
3 HTPDN 27
NU 28
NU 29
NU 30
NU 31
NU 32
SCL 33
SDA 34
NU 35
NU 36
BACKLIGHT-ADJ2 37
R3927 OPEN
NU 38
R3926 OPEN
GND 39
GND 40
GND 41
GND 42
NU 43
LCD+12V 44
C3917
LCD+12V 45
4.7
LCD+12V 46
LCD+12V 47
LCD+12V 48
LCD+12V 49
LCD+12V 50
2
LCD+12V 51
TO POWER SUPPLY
CBA CN652 CN3902
LCD+12V 6
LCD+12V 5
LCD+12V 4
GND 3
GND 2
GND 1
(NO CONNECTION) CN3903
SDA 4
SCL 3
NU 2
GND 1
CONTINUE
DIGITAL 4
R3905 OPEN
SDA1
R3906 OPEN
SCL1
BACKLIGHT-ADJ
*F:A2,A3,A5,B1~B5,B7,B8,C1~C8,D1~D4,E1,E2,E4~E6,F2,
F3,F6,F7,G1,G2,G5,G6,H1,H3~H5,J2~J6,K2~K6,L1~L3,
LD-EN
N1~N3,M3,P2~P6,R2~R6,T1,T3~T6,U1~U3,U5,U6,V2~V6,
W1~W6,Y1~Y3,Y5,Y6,AA4~AA6,AA29,AB4~AB6,AB27~AB29,
AC4,AC5,AC27,AC28,AD4,AD27~AD29,AE29,AF27~AF29,
CONTINUE AF31,AF32,AG18,AG20,AG26~AG31,AH10~AH12,AH17,AH19,
DIGITAL 8 AH20,AH28,AH29,AH31,AJ1~AJ3,AJ7~AJ13,AJ17,AJ18,
1
AJ20,AJ24~AJ26,AJ29,AJ31,AJ32,AK2~AK5,AK7~AK9,
BACKLIGHT-ADJ
AK11~AK19,AK29~AK31,AL1~AL9,AL11~AL19,AL29~AL32,
BACKLIGHT-ADJ2
AM2,AM3,AM5,AM7,AM9,AM11,AM13,AM14,AM16,AM17,AM19,
AM29,AM31,
(NO CONNECTION) CN5002
NU 1
SDA1 2
SCL1 3
GND 4
CONTINUE
DIGITAL 13
CHIP-VDET
BC
*2
IC5001(1/4)
MST7410DY
(FRAME RATE CONVERTER)
AA2
AB3
AB2
AB1
AC1
AC2
AD3
PANEL
AD2
OUTPUT
INTERFACE
AE2
AE1
AF3
AF1
AG3
AG2
AH3
AH2
R3902 100
A6 LOCKN
R3901 100
B6 HTPDN
R3920 0
R3919 OPEN
R3918 10K
R3917 OPEN
VIDEO
OUTPUT
PROCESS
R3912 OPEN
R3911 OPEN
OSD
BLENDING
V-BY-ONE
RECEIVER
C5213 R5023
10P 1.2K
AM10XTALO
2 1
X5001
R5022
24MHz
1M
3 4
AL10XTALI
C5214
10P DIGITAL
SIGNAL
PROCESS
TO DIGITAL TO DIGITAL
MAIN 11 MAIN 12
IC5001(2/4) IC5001(3/4)
AA26GND
AJ6 GND
*F NU
AH18I2CS-SDA
AG19I2CS-SCL
D7 CHIP-VDET
BD BE
2 NOTE:
The order of pins shown in this diagram is different from that of actual IC5001.
IC5001 is divided into four and shown as IC5001 (1/4) ~ IC5001 (4/4) in this Digital Main Schematic Diagram Section.
*1
IC3001(9/9)
MSD95C0H-3-002J
DIGITAL SIGNAL PROCESS
/MAIN MICRO CONTROLLER
C5182 0.1
AM20 AB36
C5183 0.1
AL20 AB35
C5184 0.1
AK20 AC36
C5185 0.1
AL21 AC37
C5186 0.1
AK21 AD37
C5187 0.1
AL22 AD36
C5188 0.1
AM22 AD35
C5189 0.1
AK22 AE36
C5190 0.1
AM23 AF36
C5191 0.1
AL23 AF37
C5192 0.1
AK23 AF35
C5193 0.1
AL24 AG37
C5194 0.1
AK24 AG35
C5195 0.1 LVDS
AL25 AH36 TX
C5196 0.1
AM25 AH35
C5197 0.1
AK25 AJ36
C5198 0.1
AM26 AJ35
C5199 0.1
AL26 AK37
C5200 0.1
AK26 AK36
C5201 0.1
AL27 AK35
C5202 0.1
AK27 AL35
C5203 0.1
AL28 AM36
C5204 0.1
AM28 AM37
C5205 0.1
AK28 AM35
R3175 100
AH24 AJ33
R3176 100
AH23 AJ34
R3173 100
AG23 AJ32
R3174 100
AJ23 AJ31
R5177 10K
NU AG24
R5178 10K
NU AH25
R5179 10K
NU AG25
R5102 10K R5187 OPEN
NU AH26
R5104 100
RESET AA28
IC5002
R5021 100
W25Q32FVSSIG
SYSTEM-CHECK D6
(MEMORY)
R5173 100
CS AE32 1
R5172 100
SOUT AE31 2
3
R5107
OPEN 4
R5183 100
UART2-TX E7
R5184 100
UART2-RX E8
R5171 100
SPI-SDA AD32
R5170 100
SPI-SCL AD31
R5005 100
UART1-TX D8
R5006 100
UART1-RX D5
BF
10-34
DIGITAL MAIN CBA UNIT
TO DIGITAL
MAIN 6
IC3001(6/9)
CONTINUE
DIGITAL 8
PANEL-POWER
CONTINUE
DIGITAL 4
SYSTEM-CHECK
FRC-RESETP
R5103 D5101
OPEN OPEN R5014 C5181
CONTINUE
10K OPEN
DIGITAL 13
CS VCC 8 FRC+3.3V
C5043
0.1
SO NU 7
WP SCL 6
R5174
10K
GND SDA 5
CN5005 (NO CONNECTION)
R5106
1 P-ON+5V
OPEN
2 UART2-TX
3 UART2-RX
C5216 4 GND
OPEN
CN5001 (NO CONNECTION)
1 P-ON+5V
2 UART1-TX
3 UART1-RX
C5056 4 GND
OPEN
BG BH
PL15.16BSCD10