S6Bt112A Cxpi Transceiver - Infineon S6BT112A Getting Started

Getting Started with CXPI Transceiver S6BT112A

S6BT112A CXPI transceiver

2 S6BT112A CXPI transceiver
The S6BT112A series is a CXPI transceiver that conforms to the JASO CXPI protocol. S6BT112A01 has a built-in
Spread Spectrum Clock Generator (SSCG), while S6BT112A02 has no SSCG. The S6BT112A series has the
following features.
Operating power supply voltage range: 5.3 V to 18 V
•
BUS breakdown voltage: ± 40 V
•
ESD breakdown voltage: HBM ± 8 kV
•
Support bitrate: 2.4 kbps ~ 20 kbps
•
The S6BT112A series employs many Cypress-proprietary EMI reduction countermeasure circuits. With these
technologies listed in Table
deploying S6BT112A to both the master node and the slave node, significant noise reduction can be obtained.
Table 1 S6BT112A EMI reduction countermeasure circuit
Feature
Optimal slew rate
control
Optimal control of duty
cycle of the master
clock
SSCG (Spread
spectrum clock
generator)
Slave bus response
timing optimization
Figure 1 shows a block diagram of the S6BT112A CXPI transceiver.
Figure 1 S6BT112A block diagram
Application Note
1, S6BT112A provides the industry's best low-noise CXPI performance. By
Measures and effects
Harmonics are reduced by lowering the slew rate.
By optimally controlling the master clock duty cycle,
harmonics in the keyless frequency band are reduced.
The noise peak level is reduced by changing the periodic
frequency of the transceiver's built-in clock slightly.
Automatically adjusts the slave to send the LOW pulse too
early or too late to reduce current noise (inductive noise). It
also reduces the noise of the keyless band.
Table 2 shows the pin functions.
4 of 19
Applicable node
Master / Slave
Master
Master
Slave
002-27376 Rev. *A
2021-06-15