Baud Rate Detection Period And Fail-Safe Decode Initialization; Baud Rate Detection Period - Infineon S6BT112A Getting Started

Getting Started with CXPI Transceiver S6BT112A
Software configuration
4.3

Baud rate detection period and fail-safe decode initialization

4.3.1

Baud rate detection period

After power-on, when the NSLP pin is set to HIGH to transition to Normal mode, S6BT112A detects the clock
cycle and initializes the LOW width of logical value '1'. Data cannot be transmitted or received during the 33 T
clock cycle detection period.
In the master node, S6BT112A starts to output the clock to BUS with an optimized duty cycle after 33 CLK
clocks. In the slave node, S6BT112A starts to output the decoded clock based on the initialized LOW width of
logical value '1' to the CLK terminal after 33 BUS clocks.
The timing chart of baud rate detection period at power on is shown in
Figure 13 Baud rate detection timing (At power ON)
After transitioning from Normal mode to Sleep mode with the power on, the NSLP pin is set to HIGH again to
transition to Normal mode. Data transmission and reception is available after transition from Standby mode to
Normal mode, using the clock cycle and the LOW width of logical value '1' detected in the previous Normal
mode.
In the master node, when S6BT112A transitions to Normal mode, it starts to transmit the clock to BUS with an
optimized duty cycle. In the slave node, when S6BT112A transitions to Normal mode, S6BT112A starts to output
the decoded clock to the CLK terminal, based on the recorded LOW width of the logical value '1'.
The timing chart of baud rate detection period while continuous power is shown in
Figure 14 Baud rate detection timing (Continuous power supply)
Application Note
Figure
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Figure 14.
002-27376 Rev. *A
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2021-06-15