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C O P 8 2 0 C J Pin A s s ig n m e n t
Port
ALT
Typ
Pin
Funct.
LO
I/O
MIWU/CMPOUT
L1
I/O
MIWU/CMPIN-
L2
I/O
MIWU/CMPIN +
L3
I/O
MIWU
L4
I/O
MIWU
L5
I/O
MIWU
L6
I/O
MIWU
L7
I/O
MIWU/MODOUT
GO
I/O
INTR
G1
I/O
G2
I/O
G3
I/O
TIO
G4
I/O
SO
G5
I/O
SK
G6
I
SI
G7
I
CKO
I0
I
1 1
I
I
I2
I
I3
DO
0
D1
0
D2
0
o
D3
Vcc
GND
CKI
RESET
Pin D e s c rip tio n
Vcc and GND are the power supply pins.
CKI is the clock input. This can come from an external
source, a R/C generated oscillator or a crystal (in conjunc
tion with CKO). See Oscillator description.
RESET is the master reset input. See Reset description.
PORT I is a 4-bit Hi-Z input port.
PORT L is an 8-bit I/O port.
There are two registers associated with the L port: a data
register and a configuration register. Therefore, each L
I/O bit can be individually configured under software control
as shown below:
16
20
28
Pin
Pin
Pin
5
7
11
6
8
12
7
9
13
8
10
14
Three data memory address locations are allocated for this
port, one each for data register [00D0], configuration regis
9
11
15
ter [00D1] and the input pins [00D2],
10
12
16
Port L has the following alternate features:
11
13
17
LO MIWU or CMPOUT
L1 MIWU or CMPIN-
12
14
18
L2 MIWU or CMPIN +
17
25
L3 MIWU
18
26
L4 MIWU (high sink current capability)
L5 MIWU (high sink current capability)
19
27
L6 MIWU (high sink current capability)
15
20
28
L7 MIWU or MODOUT (high sink current capability)
1
1
The selection of alternate Port L functions is done through
registers WKEN [00C9] to enable MIWU and CNTRL2
16
2
2
[OOCC] to enable comparator and modulator.
1
3
3
All eight L-pins have Schmitt Triggers on their inputs.
2
4
4
PORT G is an 8-bit port with 6 I/O pins (G0-G5) and 2 input
pins (G6, G7).
7
All eight G-pins have Schmitt Triggers on the inputs.
8
There are two registers associated with the G port: a data
register and a configuration register. Therefore each G port
9
bit can be individually configured under software control as
10
shown below:
19
20
21
22
4
6
6
13
15
23
Three data memory address locations are allocated for this
port, one for data register [00D3], one for configuration reg
3
5
5
ister [00D5] and one for the input pins [OOD6]. Since G6
14
16
24
and G7 are Hi-Z input only pins, any attempt by the user to
configure them as outputs by writing a one to the configura
tion register will be disregarded. Reading the G6 and G7
configuration bits will return zeros. Note that the device will
be placed in the Halt mode by writing a " 1" to the G7 data
bit.
Six pins of Port G have alternate features:
GO INTR (an external interrupt)
G3 TIO (timer/counter input/output)
G4 SO (MICROWIRE serial data output)
G5 SK (MICROWIRE clock I/O)
G6 SI (MICROWIRE serial data input)
G7 CKO crystal oscillator output (selected by mask option)
1-55
Port L
Port L
Config.
Data
0
0
Hi-Z Input (TRI-STATE)
0
1
Input with Weak Pull-up
1
0
Push-pull Zero Output
1
1
Push-pull One Output
PortG
PortG
Config.
Data
UI "7 1 nrv (TDI CTA *rr^
n
o
• ii 4 — it i|*/m yl i
0
1
Input with Weak Pull-up
1
0
Push-pull Zero Output
1
1
Push-pull One Output
or HALT restart input/general purpose input (if clock
option is R/C or external clock)
Port L
Setup
PortG
Setup
■ /-\ i
_f
l
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