Related Manuals for National Semiconductor LMH0340
Summary of Contents for National Semiconductor LMH0340
- Page 1 User Guide: SDALTEVK HSMC SDI ADAPTER BOARD 9-Jul-09 Version 0.06 SDI Development Kit using National Semiconductor’s LMH0340 serializer and LMH0341 deserializer July 2009 Rev 0.06 Page 1 of 31...
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Page 2: Table Of Contents
..Overview 3 ..Evaluation Kit (SDALTEVK) Contents ..Hardware Setup III D ..............6 YCLONE EVELOPMENT OARD OARD ESCRIPTION SDALTEVK B ......................... 8 OARD ESCRIPTION ..Software Setup ..............................9 NSTALLATION ..............................10 TARTUP ..Evaluating Hardware 13 .............................. 13 ETUPS 5.1.1 Standalone Video Generator Tests .................... -
Page 3: Overview
NTSC, PAL 720p50, 720p59, 720p60, 1080s23.98, 1080s24, 1080i50, 1080i59, 1080i60, 1080p29.97, 1080p30 1080p50, 1080p59.9, 1080p60 A user interface allows for managing the FPGA firmware functions and the LMH0340/0341/1982 device registers. Evaluation Kit (SDALTEVK) Contents The SDALTEVK contains the following parts: ... - Page 4 The following is required to complete the evaluation kit: Altera Cyclone III Development Kit Altera Part Number: DK-DEV-3C120N National Semiconductor SDI compiled .sof file from: http://www.national.com/sdaltevk o Triple Rate Standalone mode with multiple format selection o Triple Rate pass-thru mode with format detection o Pattern selection...
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Page 5: Hardware Setup
Hardware Setup The SDALTEVK printed circuit board is designed to interface with the HSMC connector on the Cyclone III Development Boards. Power, control bus, and LVDS bus signals are supplied to the daughter board through the HSMC connector. The Cyclone III FPGA provides the SD/HD/3G SDI and general purpose stacks as well as the control interface to a PC through a USB cable. -
Page 6: Cyclone Iii Development Board (Main Board) Description
Cyclone III Development Board (Main Board) Description The main board has a Cyclone III FPGA. The FPGA provides the SD/HD/3G SDI and general purpose stacks as well as the control interfaces through the supplied example firmware. The daughter board is connected to the main board through the high speed mezzanine connector (HSMC), J8. - Page 7 Figure 4 Resistors on HSCM port A Figure 5 Photograph of the back of the Cyclone III board showing location of the 100 Ohm Resistors July 2009 Rev 0.06 Page 7 of 31...
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Page 8: Sdaltevk Board Description
SDALTEVK Board Description The HSMC SDI ADAPTER board features the 5:1 LMH0340 serializer IC with integrated cable driver, the 1:5 LMH0341 deserializer IC and the LMH0344 adaptive cable equalizer IC, all highlighted in orange. These devices support SD, HD, or 3G SDI interfaces across 75 ohm coaxial cable, which can interface with the board via BNC connectors J3, J8, J10, or J13. -
Page 9: Installation
Software Setup Installation Make sure the Altera hardware is not connected to the PC. The following installation instructions are for the Windows XP Operating System. Quartus II 8.0 or newer is required to properly operate the SDALTEVK. If the terminal interface is desired then Nios II EDS 8.0 or newer must also be installed on the PC. If an older version of either Quartus II or Nios II EDS is already installed, make sure that it is updated before attempting to use the SDALTEVK. -
Page 10: Startup
Startup Make sure all the software has been installed and the hardware is powered on and connected to the PC. Run Quartus II by either by using the path “C:\altera\80\quartus\bin\quartus.exe” or selecting it from the “altera” folder in the start menu. Once the software has loaded go to the “Tools” menu, and select “Programmer.” Figure 7 Quartus Main Screen July 2009 Rev 0.06... - Page 11 This will bring up the programming window shown below. Click on the “Hardware Setup…” button, select the USB-Blaster and click Close. Use the “Add File…” button to select the appropriate bit image to program the FPGA. Make sure that the “Program/Configure” box is checked and that the “Mode” menu has JTAG selected. Press the “Start”...
- Page 12 Once the FPGA has been programmed, the SDALTEVK can be evaluated using the push button interface on the Cyclone III main board. However, if the terminal interface is desired for evaluation, run the Nios II terminal program called “nios2-terminal.exe”. This program can be found in the bin folder of the Nios II root directory, for example “C:\altera\80\nios2eds\bin\nios2-terminal.exe”.
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Page 13: Evaluating Hardware
Evaluating Hardware The EVK is designed for flexible and accurate evaluation of LMH0340 and LMH0341. Evaluation can be performed using internal or external stimuli. There is an internal pattern generator implemented in the FPGA that will generate test patterns to verify signal transmission and signal integrity. -
Page 14: Genlock Tests
4.1.2 Genlock Tests When one of the genlocked modes is selected the system is configured to use an analog sync input to generate genlocked video. The analog reference signal is applied to the EVK through BNC connector J2. If no analog reference is present, the LMH1982 has been configured to automatically switch to the on board oscillator. -
Page 15: Video Pass-Through Tests
In Pass-through Mode the EVK uses the clock recovered by the LMH0341 from the SDI input as the reference clock. The video data is then routed through the FPGA to the LMH0340 for transmission. To configure the EVK for Pass-through Mode connect the source generator to J13 of the deserializer and connect the terminating device to the serializer BNC connector J8. -
Page 16: Standalone Mode
4.2.1 Standalone Mode If Standalone Mode is selected from the main menu, a list of available video formats will appear. To select a video format enter the two digit code that appears directly to the left of the format title. Once a format is selected, the terminal will return to the main menu and the SDALTEVK will then be operating, sending a test pattern in the specified SDI video format. - Page 17 (the BNC connector labeled ‘Analog IN’). The LMH1981 extracts the sync information from this signal and passes it to the LMH1982 which generates video clocks for the FPGA, which are then used to clock the LMH0340 serializer and provide an SDI test signal output which is genlocked to the Analog input.
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Page 18: Pass-Through Mode
4.2.5 Pass Through Mode Before selecting Pass-through Mode from the main menu, apply an SD, HD or 3G SDI video signal from an external source to the SDALTEVK. When Pass-through Mode is selected from the main menu, a message will appear notifying if an input signal of a supported format is detected and return to the main menu. -
Page 19: Push Button Based Sd/Hd/3G Sdi Evaluation
Push Button Based SD/HD/3G SDI Evaluation The EVK can be configured for evaluation by using the push buttons on the Cyclone III main board only. The push button interface allows the EVK to be configured in the same modes as the terminal interface option. However, only the Nios II terminal interface allows for device and FPGA register access. -
Page 20: System Mode
4.3.2 System Mode The System Mode menu contains the various configuration options for the EVK. Use this menu to configure the EVK into one of the 3 previously discussed modes of operations. PB 0 PB 1 PB 2 PB 3 Cancel Genlock Passthrough... -
Page 21: Frequency Menu
Frequency Menu This menu configures the push buttons to cycle through supported clock frequencies. Users must select a video format with a compatible frequency in order for the system to be configured. If the system is in Standalone Mode and a valid combination is selected, the LEDs will flash once to indicate successful configuration. In other mode the video format and frequency settings are ignored. -
Page 22: Miscellaneous Registers
5.1.1 Miscellaneous Registers: Hex Address: Name Description Bits Bit Description IPT ID ID Code (1234 Hex) 15:0 ID Code 5.1.2 Reset Registers Hex Address: Name Description Bits Bit Description RESET STATUS Status bits of various 15:4 Reserved system resets Deserializer Lock Serializer Lock CPU_RST_N CPU_RST... - Page 23 Hex Address: Name Description Bits Bit Description Reserved Format Detected: 0000 0 PAL I50 0001 1 NTSC I59 0010 2 P720 50 0011 3 P720 60 0100 4 S1080 24 0101 5 I1080 50 0110 6 I1080 60 0111 7 P1080 24 1000 8 P1080 25 1001 9 P1080 30 1010 A P1080 50...
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Page 24: Datapath Registers
Hex Address: Name Description Bits Bit Description EDHAP COUNT Extended Count of EDH 15:0 16 bit Active Picture EDH error Errors count EDH FF COUNT Extended Count of EDH 15:0 16 bit Full Frame EDH error Errors count AUDIO IN Input Audio (Over SDI) 15:4 Reserved... - Page 25 Hex Address: Name Description Bits Bit Description CONTROL Selected Frequency, see RX VID FREQ for values DP AUDIO OUT Control Audio Insertion 15:8 AFN ( Audio Frame Count) Max CONTROL Module Audio control packet rate Reserved Select internal tone generator (0) or I2S input (1) Select output audio group AUDIO OUT...
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Page 26: Clocking
Hex Address: Name Description Bits Bit Description 001 1 Sweep (not implemented) 010 2 Calculated Patterns 011 3 Pulse/Bar 100 4 RP219 Pattern 101 5 SMPTE Bars Others 100% Color Bars SMPTE 352 Allows bytes 3 and 4 of the 15:8 Byte 4 INSERT... - Page 27 Hex Address: Name Description Bits Bit Description Reserved Genlock reference present Genlock No Lock Genlock No Ref Reserved Genlock frequency, as per RX VID FREQ Genlock format, as per RX VID VFORMAT Looks for Matching Reserved STATUS VFORMAT Sequences from the LMH1981 and Decodes 14:12 Decoded format type:...
- Page 28 Hex Address: Name Description Bits Bit Description Counts when timing is resynchronized July 2009 Rev 0.06 Page 28 of 31...
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Page 29: P Atterns
Supported Test Patterns The following test patterns are available from the SDI firmware in all SD, HD and 3G formats: Frequency Sweep 100% Color Bars Matrix Pathological Black Y/C Full Range Ramp Luma Ramp SMPTE 75% Color Bars SMPTE RP219 Color Bars Luma Pulse &... -
Page 30: Schematics, Boms, And Data Sheets
The reference FPGA IP source code and documentation can be found on EVK website. Up to Date Information For up to date information check this URL http://www.national.com/sdaltevk 10 Part Numbers Cyclone III Development Board: DK-DEV-3C120N http://www.altera.com/products/devkits/altera/kit-cyc3.html LMH0340/LMH0341 Evaluation Kit: SDALTEVK July 2009 Rev 0.06 Page 30 of 31... -
Page 31: July
Revision History Release Date Revisions 0.00 8-19-2008 M. Wolfe Creation 0.01 8-19-2008 M. Wolfe draft 0.02 8-25-2008 N. Unger Updated TOC Table headings Column widths 0.03 8-28-2008 N. Unger Put revision history at the end Change font of the TOC to Ariel Inserted termination resistor instructions Minor wording changes on Table 1 0.04... - Page 32 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.