NEC IE-789860-NS-EM1 User Manual page 33

CHAPTER 4
(2) Signals input from the target system via a gate
Since the following signals are input via a gate, their timing shows a delay compared to the µ PD789052, 789062,
789860, and 789861 Subseries. Refer to Figure 4-2 Equivalent Circuit 2 of Emulation Circuit.
• RESET signal
• Signals related to clock input
The X2 (CL2) pin is not used in the IE-789860-NS-EM1.
• Probe side
(Target system)
RESET
X1 (CL1)
X2 (CL2)
DIFFERENCES BETWEEN TARGET DEVICE AND TARGET INTERFACE CIRCUIT
Figure 4-2. Equivalent Circuit 2 of Emulation Circuit
100 Ω
100 Ω
OPEN
User's Manual U16499EJ1V0UM
LV
CC
4.7 kΩ
HC4066
LV
CC
HSK120
1 MΩ
HSK120
• IE system side
(IE-789860-NS-EM1)
RESET
X1
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