Timing Requirements: Serial Interface - Texas Instruments ADS866 Series Manual

ADS8664, ADS8668
SBAS492 – JULY 2015

7.6 Timing Requirements: Serial Interface

Minimum and maximum specifications are at T
AVDD = 5 V, DVDD = 3 V, V
TIMING SPECIFICATIONS
f Sampling frequency (f
S
t ADC cycle time period (f
S
f Serial clock frequency (f
SCLK
t Serial clock time period (f
SCLK
t Conversion time
CONV
t Delay time: CS falling to data enable
DZ_CSDO
t Delay time: last SCLK falling to CS rising
D_CKCS
t Delay time: CS rising to SDO going to 3-state
DZ_CSDO
TIMING REQUIREMENTS
t Acquisition time
ACQ
t Clock high time
PH_CK
t Clock low time
PL_CK
t CS high time
PH_CS
t Setup time: CS falling to SCLK falling
SU_CSCK
t Hold time: SCLK falling to (previous) data valid on SDO
HT_CKDO
t Setup time: SDO data valid to SCLK falling
SU_DOCK
t Setup time: SDI data valid to SCLK falling
SU_DICK
t Hold time: SCLK falling to (previous) data valid on SDI
HT_CKDI
t Setup time: DAISY data valid to SCLK falling
SU_DSYCK
t Hold time: SCLK falling to (previous) data valid on DAISY
HT_CKDSY
Sample
N
CS
t
SU_CSCK
1 2 7
SCLK
t
DV_CSDO
SDO
B14 B10 B9
B15
SDI
DAISY
10 Submit Documentation Feedback
= –40°C to 125°C. Typical specifications are at T
A
= 4.096 V (internal), SDO load = 20 pF, and f
REF
= max)
CLK
= max)
CLK
= max)
S
= max)
S
8 9 14 15 16
t
SU_DICK
B8 B7 B2
B3 B1 B0
Figure 1. Serial Interface Timing Diagram
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= 500 kSPS, unless otherwise noted.
SAMPLE
t
S
t
ACQ
t t
PH_CK PL_CK
17 18 23 24 25 26
t
HT_CKDO
D10 D2
D11 D5 D4 D3
#2 #2 #2 #2 #2 #2
t
Data from sample N
HT_CKDI
X X X X
X X
t
SU_DSYCK
D11 D10 D5 D4 D3 D2
#1 #1 #1 #1 #1 #1
Copyright © 2015, Texas Instruments Incorporated
ADS8664 ADS8668
= 25°C.
A
MIN TYP MAX
500
2
17
59
850
10
10
10
1150
0.4 0.6
0.4 0.6
30
30
10
25
5
5
5
5
t
PH_CS
t
t
SCLK
D_CKCS
27 28 29
30 31 32
t
t
DZ_CSDO
SU_DOCK
D1 D0
#2 #2
X
X X X X X
t
HT_CKDSY
D1 D0
#1 #1
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UNIT
kSPS
µs
MHz
ns
ns
ns
ns
ns
ns
t
SCLK
t
SCLK
ns
ns
ns
ns
ns
ns
ns
ns
Sample
N + 1