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7.8.3. Timing chart of restart from the motor output OFF state at the time of over-current
detection
L output latch state of the DIAG pin is cleared at the rising edge of EN pin and falling edge of ENB
pin.
Figure 7.8-3 Timing chart of returning from OFF state at the time of short to power supply, short
Note: Some of timing charts in this document may be omitted or simplified for explanatory purposes.
Note: This detection circuit is a function to avoid abnormal conditions such as output short-circuit,
temporarily and does not guarantee that the IC does not break. Therefore utmost care is necessary in
the design of output lines, VBAT, VCC and substrate leading of GND traces since the IC may be
destroyed by short-circuiting to the power supply or ground.
to GND, and load short
27 / 49
TB9051FTG
Ver.1.1 2019-03-14
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